MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1173

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

14.8.75 DRAM Control Register 80 (HW_DRAM_CTL80)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
DFT_CTRL_REG
W
R
31
0
Field
Field
31 0
30
0
29
0
HW_DRAM_CTL80
28
0
The Low Latency option is not functional at this time.
Bit [24] = Selects the write latency path.
'b0 = Write Data is captured 1 cycle after being sent from the MC
'b1 = Write data is captured 1/4 cycle after being sent from the MC.
The Low Latency option is not functional at this time.
Bit [23] = DFI control for Mobile MCs.
Bit [5] = Enables the pad inputs specifically for external loopback. This bit is tied to the internal signal
lpbk_rddata_en.
'b0 = Normal Operation
'b1 = Loopback Mode
Bit [4] = Enables the pad outputs specifically for external loopback. This bit is tied to the internal signal
lpbk_wrdata_en.
'b0 = Normal Operation
'b1 = Loopback Mode
Bits [3:0] = Sets the dfi_rddata_valid delay relative to dfi_rddata_en.
All other bits undefined.
Enables the PHY testing mode.
Enables the PHY testing mode. Bits [2:1] are used.
Bits [2:1] ='b10 = Normal Mode
Bits [2:1] ='b01 = Scan Mode
Currently Not Functional
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_DRAM_CTL79 field descriptions (continued)
24
0
23
0
HW_DRAM_CTL80 field descriptions
800E_0000h base + 140h offset = 800E_0140h
22
0
21
0
20
0
19
0
18
0
DFT_CTRL_REG
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
1173
0
0