MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2004

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
2004
11 10
SUSP
Field
HSP
PR
LS
9
8
7
Line Status.
These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. The bit encodings
are listed below.
In Host Mode: The use of linestate by the host controller driver is not necessary (unlike EHCI), because the
port controller state machine and the port routing manage the connection of LS and FS.
In Device Mode: The use of linestate by the device controller driver is not necessary.
0
1
2
3
High-Speed Port.
Default = 0.
When the bit is 1, the host/device connected to the port is in high-speed mode and if set to 0, the host/device
connected to the port is not in a high-speed mode.
Note: HSP is redundant with PSPD(27:26) but will remain in the design for compatibility.
This bit is not defined in the EHCI specification.
Port Reset
This field is 0 if Port Power (PP) is 0.
In Host Mode: (Read/Write).
1 = Port is in Reset.
0 = Port is not in Reset.
Default 0.
When software writes a 1 to this bit, the bus-reset sequence as defined in the USB Specification Revision
2.0 is started. This bit will automatically change to 0 after the reset sequence is complete. This behavior is
different from EHCI where the host controller driver is required to set this bit to a 0 after the reset duration
is timed in the driver.
In Device Mode: This bit is a Read-Only status bit. Device reset from the USB bus is also indicated in the
USBSTS register.
Suspend
In Host Mode: (Read/Write)
0 = Port not in suspend state.
1 = Port in suspend state.
Default = 0.
Port Enabled Bit and Suspend bit of this register define the port states as follows:
Bits Port State
0x Disable
10 Enable
11 Suspend
When in suspend state, the downstream propagation of data is blocked on this port, except for port reset.
HW_USBCTRL_PORTSC1 field descriptions (continued)
SE0 — SE0.
K_STATE — K.
J_STATE — J.
UNDEF — Undefined.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Freescale Semiconductor, Inc.