MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1323

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

If the card fails to start sending an expected response packet within 64 SCK cycles, then an
error occurrs; the command may be invalid or have a bad CRC. After the SSP detects a
time-out, it stops any DMA request activity and sets the RESP_TIMEOUT flag. If
RESP_TIMEOUT_IRQ_EN is set, then a CPU IRQ is asserted.
The SSP calculates the CRC of the received response and compares it to the CRC received
from the card. If they do not match, then the SSP sets the RESP_ERR status flag. If
RESP_ERR_IRQ_EN is set, then a CPU IRQ is asserted on a command response CRC
mismatch.
The SSP can also compare the 32-bit card status word, known as response R1, against a
reference to check for errors. If CHECK_RESP in HW_SSP_CTRL0 is set, then the SSP
XORs the response with the XOR field in the HW_SSP_COMPREF register. It then masks
the results with the MASK field in the HW_SSP_COMPMASK register. If there are any
differences between the masked response and the reference, then an error will occur. The
CPU asserts the RESP_ERR status flag. If RESP_ERR_IRQ_EN is set, then the
RESP_ERR_IRQ is asserted. In the ISR, the CPU can read the status word to see which
error flags are set.
The regular and long response tokens are shown in
17.8.2 SD/MMC Data Block Transfer
Block data is transferred on the DATA0 pin. In 1-bit I/O mode, the block data is formatted
as shown in
16-bit CRC, a Start bit, and an End bit. The block size is programmable with the
XFER_COUNT field in the HW_SSP_XFER_SIZE register. In SD/MMC mode,
WORD_LENGTH in the HW_SSP_CTRL1 register field should always be set to 8 bits.
Data is always sent Most Significant Bit of the Least Significant Byte first.
The SSP is designed to support block transfer modes only. Streaming modes may not be
supported.
Freescale Semiconductor, Inc.
CMD
CMD
Line
Line
Figure 17-11
Start
Start
Table
0
0
Table 17-4. SD/MMC Command Regular Long Response Token
Table 17-3. SD/MMC Command Regular Response Token
17-5. Block data transfers typically have 512 bytes of payload, plus a
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
0 (Card)
0 (Card)
Source
Source
shows a flowchart of SD/MMC block read and write transfers.
117-bit response
38-bit Response
Data
Data
Table 17-3
Chapter 17 Synchronous Serial Ports (SSP)
and
Table
CRC16
CRC7
CRC
CRC
17-4:
End
End
1
1
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