MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1482

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Real-Time Clock Function
The digital shadow registers will be updated (copied from analog to digital) with values
from their analog persistent counterparts under two conditions: first, whenever the chip is
powered on, and second, whenever the HW_RTC_CTRL_FORCE_UPDATE bit is set by
the software. Then, an update occurs, and all persistent registers are updated. Persistent
registers cannot be updated singly.
22.4 Real-Time Clock Function
The real-time clock is a CPU-accessible, continuously-running 32-bit counter that increments
every second and that can be derived from either the 24-MHz clock or the 32-KHz clock,
as determined by writable bit values in the RTC Persistent Register 0.
A 32-bit second counter has enough resolution to count up to 136 years with one-second
increments. The RTC can continue to count time as long as a voltage is applied to the BATT
pin, irrespective of whether the rest of the chip is powered up. The normal digital reset has
no effect on the master RTC registers located in the crystal power and clock domain. A
special first-power-on reset establishes the default value of the master RTC registers when
a voltage is first applied to the BATT pin (battery insertion).
For consistency across applications, it is recommended that the seconds timer should be
referenced to January 1, 1980 at a 32-bit value of 0 (same epoch reference as PC) in
applications that use it as a time-of-day clock. If the real-time clock function is not present
on a specific chip, as indicated in the control and status register
(HW_RTC_STAT_RTC_PRESENT), then no real-time epoch is maintained over
power-down cycles.
22.4.1 Behavior During Reset
A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See
Correct Way to Soft Reset a Block
for additional information on using the SFTRST and
CLKGATE bit fields.
22.5 Millisecond Resolution Timing Function
A millisecond counter facility is provided based on a 1-KHz signal derived from the 24-MHz
clock. The count value is neither maintained nor incremented during power-down cycles.
At each power-up, this register is set to its reset state. On each tick of the 1-KHz source,
the milliseconds counter increments. With a 32-bit counter, a kernel can run up to
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1482
Freescale Semiconductor, Inc.