MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 883

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

10.8.22 HSADC Clock Control Register (HW_CLKCTRL_HSADC)
This register controls the clock dividers that generate the High Speed ADC (HSADC) clock.
Note: Do not write register space when busy bit(s) are high.
EXAMPLE
Freescale Semiconductor, Inc.
RESET_BY_SW_
RESET_BY_SW
CLK_OUT_EN
BUSY_TIME
TIME_SEL
DIV_TIME
DISABLE
RSRVD1
RSRVD0
STATUS
SLEEP
26 21
20 19
CHIP
Field
15 0
31
30
29
28
27
18
17
16
CLOCK Gate. If set to 1, put Ethernet block in sleep mode. CLK_H_MAC0(1), CLK_H_MAC0(1)_S, and
CLK_ENET0(1)_TX are gated off. Ethernet can be wakeup remotely in sleep mode 0: Resume Ethernet
block to normal operation. CLK_H_MAC0(1), CLK_H_MAC0(1)_S, and CLK_ENET_TX are not gated. .
This bit is used to gate off all Ethernet clocks when Ethernet is disabled in some use case. If set to 1, gate
off all of the Ethernet clocks. Ethernet can not be wakeup remotely when Ethernet is disabled. 0: Do not
gate off Ethernet's clocks.
This read-only bit indicates the status of Ehternet module. 1'b1: Ethernet is in SLEEP or DISABLE mode.
1'b0: Ethernet is in NORMAL mode.
Always set to zero (0).
This read-only bit field returns a one when the clock divider is busy transfering a new divider value across
clock domains.
This field controls the divider that drives the CLK_ENET_TIME (1588 timer) domain. For changes to this
field to take effect, the reference clock must be running.
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0.
This field selects clock that drives the Ethernet 1588 timer between the xtal, ref_pll and enet_rmii_clk_in
sources.
0x0
0x1
0x2
0x3
This bit controls the ENET_CLK PAD direction. 1: Enable the output; 0: Disable the output. NOTE: This bit
must be configured before ENET PLL is enabled.
Setting this bit to a logic one will enable the function that ENET SWITCH can be reset by SW chip reset
(HW_CLKCTRL_RESET.CHIP, or watchdog_reset when HW_CLKCTRL_RESET.WDOG_POR_DISABLE
is set to 1'b1). This bit's reset value reflects OTP fuse ENET_SWITCH_RESET_BY_SW_CHIP.
Setting this bit to a logic one will enable the function that ENET SWITCH can be reset by all software reset
(Either HW_CLKCTRL_RESET.CHIP or HW_CLKCTRL_RESET.DIG). This bit's reset value reflects OTP
fuse ENET_SWITCH_RESET_BY_SW.
Always set to zero (0).
XTAL — select xtal source
PLL — select ref_pll source
RMII_CLK — select enet_rmii_clk_in source which is from PAD
UNDEFINED — Undefined
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CLKCTRL_ENET field descriptions
Description
Chapter 10 Clock Generation and Control (CLKCTRL)
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