MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1030

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
13.3.4 DCP Capability 0 Register (HW_DCP_CAPABILITY0)
This register contains additional information about the DCP module implementation
parameters.
This register provides capability information for the DCP block. It indicates the number of
channels implemented as well as the number of key storage locations available for software
use.
Address:
1030
Reset
Reset
ENABLE_TZONE
UNIQUE_KEY
NUM_KEYS
CHANNELS
DISABLE_
DECRYPT
DISABLE_
Bit
Bit
W
W
R
R
28 12
RSVD
NUM_
Field
11 8
7 0
31
30
29
31
15
0
0
HW_DCP_CAPABILITY0
RSVD[15:12]
30
14
0
0
Write to a 1 to disable decryption. This bit can only be written by secure software and the value can only be
cleared by a reset.
Write to a 1 to enable trustzone support. Channel operations initiated by secure operations will be protected
from non-secure operations and the secure channel interrupts will be routed to the secure DCP interrupt.
This bit can only be written by secure software and the value can only be cleared by a reset.
Write to a 1 to disable the per-device unique key. The device-specific hardware key may be selected by
using a value of 0xFE in the key select field.
Reserved, always set to zero.
Encoded value indicating the number of channels implemented in the design.
Encoded value indicating the number of key storage locations implemented in the design.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_DCP_CAPABILITY0 field descriptions
27
11
0
0
8002_8000h base + 30h offset = 8002_8030h
NUM_CHANNELS
26
10
0
1
25
0
0
9
24
0
0
8
Description
23
0
0
7
RSVD[28:16]
22
0
0
6
21
0
5
0
NUM_KEYS
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
1
2
17
0
0
1
16
0
0
0