MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1611
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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26.3.3 ENET-MAC Core Block Diagram
26.3.4 Ethernet MAC Frame Formats
26.3.4.1 Overview
The IEEE 802.3 Standard defines the Ethernet frame format as follows: An Ethernet frame
has a minimum length of 64 bytes and a maximum length of 1518 bytes or more if jumbo
frames are supported, excluding the preamble and the start frame delimiter bytes. An Ethernet
frame consists of the following fields:
Freescale Semiconductor, Inc.
• Seven bytes preamble
• Start frame delimiter (SFD)
• Two address fields
• Length or type field
• Data field
• Frame check sequence (CRC value)
• An EXTENSION field is defined only for gigabit Ethernet half-duplex implementations
and is not supported by the MAC core
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 26-4. ENET-MAC Core Overview
Transmit
Receive
FIFO
FIFO
Functions
Performance
Performance
Optimization
Optimization
TCP-IP
TCP-IP
TOE
Register Interface
Configuration
Satistics
CRC Check
CRC Gen
RX Control
TX Control
MAC
Pause Frame
Pause Frame
Terminate
Generate
Master
MDIO
Chapter 26 Ethernet Controller (ENET)
1611
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