MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1540

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
Address:
1540
Reset
Reset
UNAVAILABLE
Bit
Bit
Reserved
W
W
R
R
CTSEN
RTSEN
31 16
SIRLP
OUT2
OUT1
Field
RTS
DTR
RXE
TXE
LBE
6 3
15
14
13
12
11
10
9
8
7
2
31
15
0
0
HW_UARTDBG_CR
30
14
0
0
The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are
always unavailable.
CTS Hardware Flow Control Enable.
RTS Hardware Flow Control Enable.
This bit is the complement of the UART Out2 (nUARTOut2) modem status output. Not Implemented.
This bit is the complement of the UART Out1 (nUARTOut1) modem status output. Not Implemented.
Request To Send.
Data Transmit Ready. Not Implemented.
Receive Enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for
the UART signals. When the UART is disabled in the middle of reception, it completes the current character
before stopping.
Transmit Enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs
for the UART signals. When the UART is disabled in the middle of transmission, it completes the current
character before stopping.
Loop Back Enable. This feature reduces the amount of external coupling required during system test. If this
bit is set to 1, the UARTTXD path is fed through to the UARTRXD path. When this bit is set, the modem
outputs are also fed through to the modem inputs.
This bitfield is reserved.
Reserved, do not modify, read as zero.
IrDA SIR low-power mode. Not Supported.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_UARTDBG_CR field descriptions
8007_4000h base + 30h offset = 8007_4030h
RTS
27
11
0
0
DTR
26
10
0
0
RXE
25
0
1
9
UNAVAILABLE
TXE
24
0
1
8
Description
LBE
23
0
0
7
22
0
0
6
RESERVED
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0