MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1010

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
Additionally, the control logic monitors the use of CBC/hashing, so that a context reload
is not performed if the previous channel resumes an operation without an intermediate
operation from another channel.
13.2.6.3 Working with Semaphores
Each channel has a semaphore register to indicate that control packets are ready to be
processed. Several techniques can be used when programming the semaphores to control
the execution of packets within a channel. The channel will continue to execute packets as
long as the semaphore is non-zero, a chain bit is set in the descriptor and no error has
occurred.
If an error occurs, the channel issues an interrupt and clears the semaphore register. The
channel does not perform any further operations until the error bits in the status register
have been cleared. Software can manually clear a non-zero semaphore by writing 0xFF to
the CLR (clear) address of the semaphore register.
13.2.6.4 Work Packet Structure
Work packets for the DCP module are created in memory by the processor. Each work
packet includes all information required for the hardware to process the data. The general
structure of the packet is shown below.
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• Software can write the number of pending packets into the semaphore register with the
• Software can create a packet chain with the Decrement Semaphore bit set only in the
• Software can create a packet chain with the Decrement Semaphore bit set for each
Decrement Semaphore bit in each control packet set. In this scenario, the channel simply
decrements the semaphore for each packet set and terminates at the end of the packet
chain. The benefit of this method is that software can easily determine how many
packets have executed by reading the semaphore status register.
last packet. In this case, software would write a 1 to the semaphore register to start the
chains and the DCP will terminate after executing the last packet.
packet and write either a 1 or a number less than the number of packets to the semaphore
register. This can be useful when debugging, because it allows the channel to execute
only a portion of the packets and software can inspect intermediate values before
restarting the channel again.
Word0
Word1
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 13-2. DCP Work Packet Structure
Next Cmd Addr
Control0
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