MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1647

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

26.3.14.3 Transmit FIFO
Four programmable thresholds are available which are programmed with registers
TX_ALMOST_EMPTY, TX_ALMOST_FULL, TX_SECTION_EMPTY and TFWR /
STR_FWD.
Freescale Semiconductor, Inc.
TX_SECTION_EMPTY
TX_ALMOST_EMPTY
TX_ALMOST_FULL
TFWR / STR_FWD
Register
end-of-frame is available for the frame, the MAC transmit logic, to avoid FIFO underflow, stops reading
truncates the current frame and sets the error status. As a result the frame will be transmitted with an
When the FIFO level reaches the value programmed in the register TX_SECTION_EMPTY, the Core
When the FIFO level reaches the value coded in the register TFWR and when the register bit STR_FWD
is set to '0', the MAC transmit control logic starts frame transmission even before the end-of-frame is
A minimum value of 4 should be set. Larger values allow more latency for the application to react on
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
A typical setting is 8, which offers 3-4 clock cycles of latency to the application to react on ff_tx_rdy
To enable store and forward on the Transmit path, set the register bit STR_FWD to '1'. In this case,
When the FIFO level reaches the value programmed in the register TX_ALMOST_EMPTY, and no
If the application does not react on this signal, the FIFO write control logic, to avoid FIFO overflow,
This gives the application an indication to slow down or stop its write transaction to avoid a buffer
If a complete frame has a size smaller than the threshold programmed with TFWR, the MAC also
Table 26-24. Transmit FIFO Thresholds Definition
When the FIFO level comes close to the maximum, so that there is no more space for at least
the MAC starts to transmit data only when a complete frame is stored in the Transmit FIFO.
This is a pure indication function to the application. It has no effect within the MAC.
status ff_tx_septy is deasserted to indicate that the Transmit FIFO is getting full.
TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted.
the FIFO and transmits the Ethernet frame with a MII error indication.
ff_tx_rdy deassertion, before the frame is being truncated.
When a value of 0 is set, the signal is never deasserted.
available in the FIFO (cut-through operation).
A minimum value of 4 should be set.
transmits the Frame to the line.
MII error indication.
deassertion.
Description
overflow.
Chapter 26 Ethernet Controller (ENET)
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