MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2003
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 2003 of 2327
- Download datasheet (17Mb)
Freescale Semiconductor, Inc.
15 14
Field
PIC
PO
PP
13
12
Any other value than 0 indicates that the port is operating in test mode. Refer to Chapter 9 of the USB
Specification Revision 2.0 for details on each test mode.
The TEST_FORCE_ENABLE_FS and TEST_FORCE_ENABLE_LS are extensions to the test mode support
specified in the EHCI specification.
Writing the PTC field to any of the TEST_FORCE_ENABLE_{HS/FS/LS} values will force the port into the
connected and enabled state at the selected speed. Writing the PTC field back to TEST_DISABLE will allow
the port state machines to progress normally from that point.
Note: Low speed operations are not supported.
0
1
2
3
4
5
6
7
Port Indicator Control.
Default = 0.
Refer to the USB Specification Revision 2.0 for a description on how these bits are to be used.
0
1
2
3
Port Owner.
Port owner handoff is not implemented in this design, therefore this bit will always read back as 0.
The EHCI definition is include here for reference:
Default = 0.
This bit unconditionally goes to a 0 when the configured bit in the CONFIGFLAG register makes a 0 to 1
transition.
This bit unconditionally goes to 1 whenever the Configured bit is 0.
System software uses this field to release ownership of the port to a selected host controller (in the event
that the attached device is not a high-speed device).
Software writes a 1 to this bit when the attached device is not a high-speed device. A 1 in this bit means
that an internal companion controller owns and controls the port.
Port Power (PP).
This bit represents the current setting of the switch (0=off, 1=on).
When power is not available on a port (i.e., PP equals a 0), the port is nonfunctional and will not report
attaches, detaches, etc.
When an over-current condition is detected on a powered port, the PP bit in each affected port may be
transitioned by the host controller driver from a 1 to a 0 (removing power from the port).
This feature is implemented in the host/OTG controller (PPC = 1). In a device implementation, port power
control is not necessary.
HW_USBCTRL_PORTSC1 field descriptions (continued)
TEST_DISABLE — Disable.
TEST_J_STATE — J-State.
TEST_K_STATE — K-State.
TEST_J_SE0_NAK — Host:SE0/Dev:NAK.
TEST_PACKET — Test-Packet.
TEST_FORCE_ENABLE_HS — Force-Enable-HS.
TEST_FORCE_ENABLE_FS — Force-Enable-FS.
TEST_FORCE_ENABLE_LS — Force-Enable-LS.
OFF — OFF.
AMBER — Amber.
GREEN — Green.
UNDEF — undefined.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 31 USB High-Speed On-the-Go Host Device Controller
Description
2003
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