MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1241

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Since current NAND Flash does not support multiple page read/write commands, the GPMI
and DMA have been designed to handle complex multi-page operations without CPU
intervention. The DMA uses a linked descriptor function with branching capability to
automatically handle all of the operations needed to read/write multiple pages:
15.2.1 Multiple NAND Support
The GPMI supports up to eight NAND chip selects, each with independent ready/busy
signals. Since they share a data bus and control lines, the GPMI can only actively
communicate with a single NAND at a time. However, all NANDs can concurrently perform
internal read, write, or erase operations. With fast NAND Flash and software support for
concurrent NAND operations, this architecture allows the total throughput to approach the
data bus speed, which can be as high as 50 MB/s (8-bit bus running at 50 MHz).
There are two options for controlling the eight NAND chip selects through the DMA
interface. The first option is one to one mapping, where each DMA channel is attached to
its own NAND. For example DMA channel 'n' accesses only NAND attached to chip select
'n'. The second option is the decoupled mode where a DMA channel can access any or all
NANDs connected to the GPMI. A DMA channel will signify the NAND it wants to access
by writing its chip select value in the HW_GPMI_CTRL0_CS field and setting the
HW_GPMI_CTRL1_DECOUPLE_CS to '1'. This option is useful if software chooses to
use only one DMA channel to access all the attached NAND devices.
15.2.2 GPMI NAND Timing and Clocking
The dedicated clock, GPMICLK, is used as a timing reference for NAND Flash I/O. Since
various NANDs have different timing requirements, GPMICLK may need to be adjusted
for each application. While the actual pin timings are limited by the NAND chips used, the
Freescale Semiconductor, Inc.
• Data/Register Read/Write The GPMI can be programmed to read or write multiple
• Wait for NAND Ready The GPMI's Wait-for-Ready mode can monitor the ready/busy
• Check Status The Read-and-Compare mode allows the GPMI to check NAND status
cycles to the NAND address, command or data registers.
signal of a single NAND Flash and signal the DMA when the device has become ready.
It also has a time-out counter and can indicate to the DMA that a time-out error has
occurred. The DMAs can conditionally branch to a different descriptor in the case of
an error.
against a reference. If an error is found, the GPMI can instruct the DMA to branch to
an alternate descriptor, which attempts to fix the problem or asserts a CPU IRQ.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 15 General-Purpose Media Interface(GPMI)
1241