MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2064

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
33.2.3 Read Datapath
The above figure shows the MPU read datapath in detail. LCDIF can read from an external
LCD controller or any other device that follows the 6800/8080 MPU protocol. The size of
the data read at a time on the interface is determined by the LCD_DATABUS_WIDTH
bitfield. The data grabbed at every read strobe is called a subword and the number of
subwords that can be packed in a 32-bit word is given by the
READ_MODE_NUM_PACKED_SUBWORDS bitfield. Setting a non-zero value in the
INITIAL_DUMMY_READ bitfield indicates to LCDIF to skip that many number of
subwords before starting to record the read data. This feature is useful in the case of an LCD
controller that returns the last written data the first time a read is issued, and then sends the
correct data after that point. SHIFT_DIR and SHIFT_NUM_BITS bitfields indicate whether
the data needs to be shifted before getting stored in the internal registers. For example, a
value of 2 in READ_MODE_NUM_PACKED_SUBWORDS if lcd databus width is 8 bits
indicates two bytes should be packed in a 32-bit word, while if the lcd databus width is 16
bits, it indicates that two half words (or 4 bytes) should be packed.
After the last subword within a word is reached, the block looks at the READ_PACK_DIR
in the HW_LCDIF_CTRL2 register. If this bit is set, the block will swizzle the data, but
only within the valid bytes, unlike in the write mode, where swizzle occurs across all 4
bytes. If the READ_MODE_OUTPUT_IN_RGB_FORMAT bit is set, LCDIF will convert
the data obtained from the READ_PACK_DIR operation into 24-bit unpacked RGB and
then re-convert it into 16/18/24 bpp RGB depending on the WORD_LENGTH field. The
DATA_FORMAT_16/18/24_BIT bitfields are also considered while converting to 24-bit
unpacked RGB format. For example, if DATA_FORMAT_18_BIT is 1, the RGB666 data
will be packed in the upper bits [31:4]of a 32-bit word, and that bit is 0, the data will be
packed in the lower bits [17:0]. After all these operations, the data gets written into the
RXFIFO.
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LCD DMA
Control
Figure 33-7. 16-Bit LCDIF Register Programming-Example B
32
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Swizzle
Read Control
Calculation
Count
HCLK Domain
32
RXFIFO
32x16
CLK_DIS_LCDIFn Domain
32
FIFO Status
32
Write Control
32
32
32
32
32
Temp Reg and Valid
Subword Packing
Transfer
RGB to
Control
Shifting
RGB
CSC
8/16
8/16
Freescale Semiconductor, Inc.
8/16
Signal
Gen
LCD Data
LCD Control
8/16/18/24