MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1053

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

13.3.28 DCP Channel 3 Command Pointer Address Register
The DCP channel 3 current command address register points to the multiword descriptor
that is to be executed (or currently being executed). The channel may be activated by writing
the command pointer address to a valid descriptor in memory and then updating the
semaphore to a non-zero value. After the engine completes processing of a descriptor, the
next_ptr field from the descriptor is moved into this register to enable processing of the
next descriptor. All channels with a non-zero semaphore value will arbitrate for access to
the engine for the subsequent operation.
DCP Channel 3 is controlled by a variable sized command structure. This register points
to the command structure to be executed.
EXAMPLE
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
pointer
R
RECOVERY_
31
0
TIMER
31 16
RSVD
ADDR
Field
15 0
Field
31 0
30
0
29
0
pCurptr = (hw_DCP_chn_cmdptr_t *) HW_DCP_CHn_CMDPTR_RD(3);
HW_DCP_CHn_CMDPTR_WR(3, v);
HW_DCP_CH3CMDPTR
(HW_DCP_CH3CMDPTR)
28
0
Reserved, always set to zero.
This field indicates the recovery time for the channel. After each operation, the recover timer for the channel
is initiallized with this value and then decremented until the timer reaches zero. The channel will not initiate
operation on the next packet in the chain until the recovery time has been satisfied. The timebase for the
recovery timer is 16 HCLK clock cycles, providing a range of 0ns to 8.3ms at 133 MHz operation.
Pointer to descriptor structure to be processed for channel 3.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
HW_DCP_CH3CMDPTR field descriptions
23
0
HW_DCP_CH2OPTS field descriptions
22
0
8002_8000h base + 1C0h offset = 8002_81C0h
21
0
20
0
19
0
18
0
// Write channel 3 command pointer
17
0
ADDR
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
Chapter 13 Data Co-Processor (DCP)
0
9
0
8
// Read current command
0
7
0
6
0
5
0
4
3
0
0
2
0
1
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0
0