dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 78

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Data Types and Addressing Modes
3.6.2
The register-direct addressing modes specify that each of up to three operands is in either the AGU, data
ALU, or control registers. This type of reference is classified as a register reference.
In Example 3-8, two operands are specified with the register-direct addressing mode. The source operand,
R0, is in the AGU, and the destination operand, X0, is in the data ALU.
3.6.3
In the address-register-indirect addressing modes, the operand is not the address register itself, but consists
of the contents of the memory location that is pointed to by the address register. Most
address-register-indirect modes also allow the pointer register to be updated in some way. The
addressing mode, for example, accesses the memory location indicated by the address register and then
subtracts one from the register, when the register is used as a word pointer accessing a 16-bit word.
Note that the arithmetic performed can differ depending on the data type. In Example 3-9, the R5 register
is post-incremented by one for a byte or word access and by two for a long memory access.
In the MOVE.L instruction in Example 3-10, the assembler right shifts the offset of “6” when encoding the
value. When executing the instruction, the AGU unit then left shifts the value in hardware to generate a
displacement of 6 (that is, 3 long words) from the SP. See Section 6.7, “AGU Arithmetic Instructions,” on
page 6-18 for detailed information on how arithmetic is performed for different data types and addressing
modes.
The type of arithmetic (linear or modulo) used for calculating the effective address in R0 or R1 is specified
in the modifier register (M01) rather than encoded in the instruction. Modulo arithmetic is covered in detail
in Section 6.8, “Linear and Modulo Address Arithmetic,” on page 6-20.
The remainder of this section illustrates each address-register-indirect addressing mode.
3-28
Register-Direct Modes
Address-Register-Indirect Modes
MOVE.W
MOVE.BP
MOVE.W
MOVE.L
MOVE.W
MOVE.L
There can be pipeline dependencies when a data ALU, AGU, or control
register is being accessed. Refer to Section 10.4, “Pipeline Dependencies
and Interlocks,” on page 10-26 to understand dependencies when
accessing these registers.
Example 3-10. Effects of Data Types on Address Displacements
Example 3-8. Using the Register-Direct Addressing Mode
Example 3-9. Effects of Data Types on AGU Arithmetic
R0,X0
X:(R5)+,A
X:(R5)+,A
X:(R5)+,A
X:(SP–3),A
X:(SP–6),A
DSP56800E Core Reference Manual
; Operands are registers
; Byte Access: R5 <= R5 + 1
; Word Access: R5 <= R5 + 1
; Long Access: R5 <= R5 + 2
; Access 3rd word from SP
; Access 3rd long from SP
NOTE:
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X:(Rn)-