dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 680

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dsp56800e

Manufacturer Part Number
dsp56800e
Description
16-bit Digital Signal Controller Core
Manufacturer
Freescale Semiconductor, Inc
Datasheet
The following bits are only affected by the condition code mode in unusual cases:
The condition code mode does not affect any of the test and comparison instructions, such as TST.W and
CMP.BP. The condition code mode also only affects operations performed in the data ALU. It does not
affect operations that are performed outside the data ALU, such as move instructions, bit-manipulation
instructions, and AGU instructions.
B.2
A description of each of the bits in the status register is given in the following sections. Each description
given is the standard definition for each condition code bit, but the bits might be set or cleared slightly
differently depending on the instruction being executed. For the exact calculation for a given instruction,
see Section B.3, “Condition Code Summary by Instruction.”
The condition code register occupies the low-order 8 bits of the status register (SR).
SR
B-4
RESET
SZ
Bit 7
L
Bit 6
E
Bit 5
U
Bit 4
N
Bit 3
TYPE
Name
BIT 15
L—May be indirectly affected through effects on V bit
N—Only affected by ASRAC, LSRAC, IMPY.W, and ASLL.W
C—Only affected by ASL
LF
rw
0
Condition Code Register
Size—Indicates growth beyond a certain point in
the size of an accumulator value
Limit—Indicates whether data limiting has been
performed since this bit was last cleared
Extension in Use—Indicates whether an accu-
mulator extension register is in use
Unnormalized—Shows whether a result value
is normalized or not
Negative—Indicates whether result of last oper-
ation was negative or positive
14
P4
0
r
Because of enhancements to the instruction set, it is generally not
necessary to operate the DSC in 32-bit condition code mode. New
instructions support test and compare operations for byte, word, and long
data types, as well as for full 36-bit accumulators. New applications should
not use 32-bit condition code mode.
P3
13
0
r
P2
12
0
r
Table B-1. Condition Code Bit Descriptions
Description
P1
11
DSP56800E Core Reference Manual
0
r
10
P0
0
r
Status Register
rw
I1
9
1
NOTE:
rw
I0
8
1
SZ
rw
7
0
0 = Accumulator value is small.
1 = Accumulator value is large.
0 = No limiting performed.
1 = Limiting has been performed.
0 = Extension not in use.
1 = Extension in use.
0 = Normalized.
1 = Not normalized.
0 = Result was positive.
1 = Result was negative.
rw
6
L
0
rw
E
5
0
1
rw
U
4
0
Settings
Freescale Semiconductor
rw
N
3
0
rw
2
Z
0
rw
V
1
0
BIT 0
rw
C
0

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