dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 150

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Data Arithmetic Logic Unit
The data registers are used as source or destination operands for most data ALU operations. With the use
of parallel move instructions (see Section 3.3.5, “Parallel Moves,” on page 3-11), these registers can serve
as sources for data ALU operations while new operands are loaded into them, in parallel, from memory.
This process is demonstrated in Example 5-1.
The Y1, Y0, and X0 registers can be read or written as a byte or word operand. The Y register is read or
written as a long operand. All of the registers can be read or written using a parallel move. Only the X0
register can be written by the secondary read in a dual read instruction.
5.1.2
The data ALU contains four, independent, 36-bit accumulator registers that serve as the source or
destination for operations in the data ALU.
Each 36-bit data ALU accumulator register is composed of three different portions:
The “FF” notation is used throughout this chapter and the rest of the manual in references to the
accumulators. In this notation, FF refers to the entire accumulator (bits 35–0), FF2 refers only to the 4-bit
extension portion (bits 35–32), FF1 is the 16-bit most significant portion (bits 31–16), and FF0 is the 16-bit
least significant portion (bits 15–0). The various parts of an accumulator and the corresponding “FF”
notation are shown in Figure 5-4. Note that there is not actually an “FF” accumulator anywhere in the chip.
5-4
•
•
•
Extension (FF2)
4-bit extension register, FF2 (where FF2 represents A2, B2, C2, or D2)
16-bit most significant product (MSP), FF1 (where FF1 represents A1, B1, C1, or D1)
16-bit least significant product (LSP), FF0 (where FF0 represents A0, B0, C0, or D0)
Accumulator Registers (A, B, C, D)
ADD.W
Figure 5-4. Different Components of an Accumulator (Using “FF” Notation)
Figure 5-3. The 32-Bit Y Register—Composed of Y1 Concatenated with Y0
FF
Example 5-1. X0 Register Used in Operation and Loaded in Parallel
Y
35
31
X0,A
FF2
32 31
X:(R0)+,X0
DSP56800E Core Reference Manual
Y1
MSP
FF1
16 15
; X0 used and simultaneously loaded
MSP (FF1)
16 15
32-Bit Y Register
Entire Accumulator (FF)
Y0
Long Portion of Accumulator (FF10)
LSP
FF0
0
LSP (FF0)
Freescale Semiconductor
0