dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 283

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Note that memory accesses take place across three stages of the pipeline: an address is provided in the first
cycle of an access, the memory latches the address on the second cycle, and the memory drives the
corresponding data bus on the third cycle. This requirement applies when accessing both program and data
memory, and when fetching both instructions and operands.
10.2
Normal instruction execution occurs in an eight-stage pipeline, allowing most instructions to be retired at a
rate of one instruction per clock cycle. Certain instructions, however, require more than 1 clock cycle to
complete. These include the following:
10.2.1
Pipelining allows instruction executions to overlap so that the execution of one pipeline stage for a given
instruction occurs concurrently with the execution of other pipeline stages for other instructions. The
processor fetches only 1 instruction word per clock cycle; if an instruction is more than 1 instruction word
in length, it fetches each additional word with an additional cycle before fetching the next instruction.
Table 10-2 on page 10-4 demonstrates simultaneous execution through the pipelining of the five
instructions that are found in Example 10-1 on page 10-4.
Freescale Semiconductor
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Instructions longer than 1 instruction word
Instructions using an addressing mode that requires more than 1 cycle for the address calculation
Data ALU arithmetic instructions with one operand in memory
Instructions causing a change of flow
Instructions accessing program memory
Special instructions:
— Multi-bit shifting instructions that operate on 32-bit values
— TSTDECA.W instruction
— NORM instruction
— ALIGNSP instruction
— REP instruction
Normal Pipeline Operation
General Pipeline Operations
Table 10-1. Mapping Fundamental Operations to Pipeline Stages
Instruction fetch
Data memory access
AGU calculation
Data ALU calculation—Normal
Data ALU calculation—Late
Data ALU calculation—multiplication and shifts
Operation
Instruction Pipeline
Pipeline Stages
AG, OP2, EX
P1, P2, IF
EX, EX2
EX2
AG
EX
Normal Pipeline Operation
10-3