dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 109

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

reflected in the total cycle count for each change-of-flow instruction. A special group of instructions
referred to as “delayed” instructions provide a mechanism for executing useful tasks during these normally
wasted cycles.
4.3.1
The delayed instructions use the execution pipeline more efficiently by executing one or more of the
instructions following the delayed instruction before execution is switched to the target address. The
number of instructions is limited by the number of delay slots that are available with a given delayed
instruction, where each delay slot consists of 1 program word.
The delayed instructions, and the number of delay slots for each, are shown in Table 4-13.
The delay slots following each of these instructions must be filled with exactly the same number of
instruction words as there are delay slots. If not all delay slots can be filled with valid instructions, then
each unused delay slot must be filled with an NOP instruction. If a pipeline dependency occurs due to
instructions executed in the delay slots, the appropriate amount of interlock cycles are inserted by the core,
reducing the number of delay-slot cycles that are available for instructions by the same number of cycles.
See Section 10.4, “Pipeline Dependencies and Interlocks,” on page 10-26 for more information.
Example 4-2 shows a code fragment that reverses the contents of a buffer in memory that starts at the
address contained in R0. Note the BRA instruction that is used to return to the top of the loop. Due to the
design of the execution pipeline, the pipeline stalls for 2 cycles while control is transferred back to the top
of the loop.
SWAP_LOOP
DONE
A more efficient way to implement the reversal algorithm is to use the BRAD instruction instead of BRA.
Example 4-3 on page 4-14 shows BRAD being used, with the code rearranged appropriately. By using
BRAD, we can execute the two MOVE.W instructions during the 2 cycles that would normally be wasted
due to the branch.
Freescale Semiconductor
Using Delayed Instructions
ADDA
CMPA
BLE
MOVE.W
MOVE.W
BRA
...
#buflen-1,R0,R1
R0,R1
DONE
X:(R0)+,X0
X0,X:(R1)-
SWAP_LOOP
Example 4-2. Code Fragment with Regular Branch
Delayed Instructions
Table 4-13. Delayed Instructions
FRTID
BRAD
JMPD
RTSD
RTID
Instruction Set Introduction
; put end of buffer in R1
; check if done yet
; if R0 >= R1, we’re done
; perform the swap
;
; branch back to top of loop
; pipeline stalls for 2 cycles
; subsequent code...
"
Number of Delay Slots
"
"
Delayed Flow Control Instructions
2
2
3
3
2
4-13