dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 49

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

2.5.1
Program memory (RAM or ROM) can be provided on-chip with the DSP56800E architecture. The PAB
bus is used to select program memory addresses; instruction fetches are performed over the PDB. Writes of
16-bit data to program memory are supported over the CDBW bus.
The interrupt and reset vector table can be any size and located anywhere in program memory. The size of
the table is determined by the number of peripherals on the device and by the requirements of the particular
application.
Program memory can be expanded off-chip, with a maximum of 2
2.5.2
On-chip data memory (RAM or ROM) can be implemented on a DSP56800E device. Addresses in data
memory are selected on the XAB1 and XAB2 buses. Byte, word, and long data transfers occur on the
CDBR and CDBW buses. A second 16-bit read operation can be performed in parallel on the XDB2 bus.
Peripheral registers are memory mapped into the data memory space. The instruction set optimizes access
to the peripheral registers with a special peripheral addressing mode that makes access to a 64-location
peripheral address space more efficient. Although the peripheral register address range is typically from
$00FFC0 to $00FFFF, individual DSP56800E devices may locate it anywhere in the data memory address
space. The top 12 locations of the peripheral register address space are reserved by the system architecture
for the core, interrupt priority, and bus control configuration registers.
A special addressing mode also exists for the first 64 locations in data memory. Like the peripheral
addressing mode, these locations can be accessed using single word, single cycle instructions. For more
information on these and other addressing modes used to access data memory, see Section 3.6.5.1,
“Absolute Short Address: aa,” on page 3-42.
Data memory can be expanded off-chip, with a maximum of 2
Freescale Semiconductor
ADR
DATA
Program Memory
Data Memory
24
32
Figure 2-5. Example of Chip Based on DSP56800E Core
External Bus
32K × 16
Interface
JTAG
ROM
PLL
Core Architecture Overview
DSP56800E
16-Bit
Core
DSC
24
(16M) addressable locations.
21
Blocks Outside the DSP56800E Core
COP & Real-
Time Timer
(2M) addressable locations.
4K × 16
Timers
XRAM
Serial
GPIO
IRQA
IRQB
AA0002
2-11