dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 607

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

SBC
Operation:
D – S – C → D
Description: Subtract the source operand (S) and the carry bit (C) from the second operand, and store the result in
Usage:
Example:
Explanation of Example:
Note:
Condition Codes Affected:
Freescale Semiconductor
Before Execution
A2
0
the destination (D). The source operand (S) is always register Y, which is first sign extended internally
to form a 36-bit value before being subtracted from the destination accumulator. The result is not af-
fected by the state of the saturation bit (SA).
This instruction is typically used in multi-precision subtraction operations (see Section 5.5.1, “Extend-
ed-Precision Addition and Subtraction,” on page 5-29) when it is necessary to subtract together two
numbers that are larger than 32 bits, as in 64-bit or 96-bit subtraction.
SBC
Prior to execution, the 32-bit Y register—which is composed of the Y1 and Y0 registers—contains the
value $3FFF:FFFE, and the 36-bit accumulator contains the value $0:4000:0000. In addition, the initial
value of C is one. The SBC instruction automatically sign extends the 32-bit Y registers to 36 bits and
subtracts this value from the 36-bit accumulator. The carry bit (C) is also subtracted from the LSB of
this 36-bit operation. The 36-bit result is stored back in the A accumulator, and the condition codes are
set appropriately. The Y1:Y0 register pair is not affected by this instruction.
C is set correctly for multi-precision arithmetic, using long-word operands only when the extension
register of the destination accumulator (FF2) contains only sign extension information (bits 31 through
35 are identical in the destination accumulator).
L
E
U
N
Z
V
C
LF
15
— Set if overflow has occurred in result
— Set if the extension portion of accumulator result is in use
— Set according to the standard definition of the U bit
— Set if bit 35 of accumulator result is set
— Set if accumulator result equals zero; cleared otherwise
— Set if overflow has occurred in accumulator result
— Set if a carry (or borrow) occurs from bit 35 of accumulator result
(no parallel move)
3FFF
4000
P4
14
A1
Y1
Y,A
13
P3
SR
P2
12
MR
Subtract Long with Carry
P1
11
FFFE
0000
0301
A0
Y0
P0
10
Instruction Set Details
; subtract Y and carry bit from A
I1
9
Assembler Syntax:
SBC
I0
8
SZ
7
After Execution
6
L
A2
0
5
E
S,D
U
4
CCR
3FFF
0000
A1
Y1
N
3
(no parallel move)
SR
2
Z
V
1
FFFE
0001
0310
C
0
A0
Y0
SBC
A-263