dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 683

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

B.2.6
The zero bit (Z) is set if the result of a data ALU or an AGU operation is zero. A value is zero if all
significant bits are clear. The accumulator extension registers are not checked if 32-bit condition code
mode is active.
B.2.7
The overflow bit (V) is set if an arithmetic overflow occurs in the result of a data ALU operation. Overflow
occurs when the carry into the result’s MSB is not equal to the carry out of the MSB. This inequality
indicates that the result of the ALU operation is not representable in the destination and that the result has
overflowed. The V bit is set based on the size of the destination operand, not on the internally calculated
(20- or 36-bit) value. If 32-bit condition code mode is selected, the extension portion of the destination is
ignored.
When saturation is enabled (SA = 1), V is set when saturation occurs. If saturation does not occur, the
preceding rules determine the V bit.
B.2.8
The carry bit (C) is set if a carry is generated out of the most significant bit (MSB) of the result for an
addition, or if a borrow is generated in a subtraction. It is cleared otherwise. C is always calculated based
on a carry or borrow out of the high-order bit (bit 31 for a 32-bit result). Note that for 20- and 36-bit
accumulator results, this bit will always be bit 35.
C is also used by a number of instructions to indicate conditions other than a carry out. The shift and rotate
instructions place the bit that is shifted or rotated out of the destination into the carry bit. The C bit is also
used by the bit-manipulation instructions to indicate the status of a bitfield comparison. See Table B-3 on
page B-9 for more information.
Freescale Semiconductor
Zero Bit (Z)
Overflow Bit (V)
Carry Bit (C)
Condition Code Calculation
B-7