dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 566

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

MPYSU
Operation:
S1 × S2 → D
Description: Multiply one signed 16-bit source operand by one unsigned 16-bit operand, and place the 32-bit frac-
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
A-222
Before Execution
A2
0
tional product in the destination (D). The order of the registers is important. The first source register
(S1) must contain the signed value, and the second source (S2) must contain the unsigned value to pro-
duce correct fractional results. If the destination is one of the 16-bit registers, only the high-order
16 bits of the fractional result are stored. The result is not affected by the state of the saturation bit
(SA). Note that for 16-bit destinations, the sign bit may be lost for large fractional magnitudes.
In addition to single-precision multiplication of a signed value times an unsigned value, this instruction
is also used for multi-precision multiplications, as shown in Section 5.5, “Extended- and Multi-Preci-
sion Operations,” on page 5-29.
MPYSU
Prior to execution, the 16-bit X0 register contains the (signed) negative value $FFF4, and the 16-bit
Y0 register contains the (unsigned) positive value $0002. The contents of the destination register are
not important prior to execution because they have no effect on the calculated value. Execution of the
MPYSU instruction multiplies the 16-bit signed value in the X0 register by the 16-bit unsigned value
in Y0 (yielding the fractional product result of $FFFF:FFD0) and stores the signed result
($F:FFFF:FFD0) back into the A accumulator.
L
E
U
N
Z
V
LF
15
— Set if overflow has occurred in result
— Set if the extended portion of the result is in use
— Set according to the standard definition of the U bit
— Set if MSB of result is set
— Set if result equals zero
— Set if overflow has occurred in result
(S1 signed; S2 unsigned)
0000
2000
P4
14
A1
Y1
X0,Y0,A
13
P3
X0
SR
P2
12
Signed × Unsigned Multiply
MR
DSP56800E Core Reference Manual
P1
11
FFF4
0000
0002
0300
A0
Y0
P0
10
; multiply signed X0 by unsigned Y0
; and store the result in A
I1
9
Assembler Syntax:
MPYSU
I0
8
SZ
7
After Execution
6
L
A2
F
5
E
S1,S2,D
U
4
CCR
FFFF
2000
A1
Y1
N
3
SR
X0
2
Z
Freescale Semiconductor
(no parallel move)
V
1
FFD0
FFF4
0002
0318
C
0
A0
Y0
MPYSU