dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 488

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

IMACUU
Operation:
D + (S1 × S2) → D
Description: Multiply the two unsigned 16-bit source operands (S1 and S2), and add the 32-bit integer product to
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Instruction Fields:
Instruction Opcodes:
Timing:
Memory:
A-144
IMACUU q1.l,q2.h,Y
Operation
IMACUU
Before Execution
B2
A2
0
0
the destination (D). The destination for this instruction is always the Y register. The result is not af-
fected by the state of the saturation bit (SA).
This instruction is used to perform extended-precision multiplication calculations. It provides a meth-
od for calculating one of the intermediate values that is needed when a 32-bit × 32-bit multiplication
is performed, for example. See Section 5.5.3, “Multi-Precision Integer Multiplication,” on page 5-32
for an example that uses the IMACUU instruction.
IMACUU A0,B1,Y
Prior to execution, the A accumulator contains the value $0:FFFF:0002, the B accumulator contains
$0:FFFE:1234, and the 32-bit Y register contains $0000:0004. Execution of the IMACUU instruction
multiplies the 16-bit unsigned value in A0 by the 16-bit unsigned value in B1, adds the resulting 32-bit
product to the 32-bit Y register, and stores the 32-bit unsigned result ($0002:0000) into Y.
The condition codes are not modified by this instruction.
1 oscillator clock cycle
1 program word
(S1 unsigned; S2 unsigned)
FFFE
FFFF
0000
B1
Y1
A1
Operands
Integer MAC Two Unsigned Values
C0,C1,Y
C0,D1,Y
A0,A1,Y
A0,B1,Y
A0,C1,Y
A0,D1,Y
B0,C1,Y
B0,D1,Y
DSP56800E Core Reference Manual
1234
0004
0002
B0
Y0
A0
15
0
1
; multiply unsigned in A0 and B1, add to Y
C
1
1
Assembler Syntax:
IMACUU
W
1
12
1
Integer 16 × 16 multiply-accumulate:
F0 (unsigned) × F1 (unsigned)
11
0
After Execution
0
B2
A2
0
0
1
S1,S2,D
1
8
FFFE
FFFF
0002
B1
Y1
A1
7
1
Comments
q
Freescale Semiconductor
q
(no parallel move)
IMACUU
q
4
1234
0000
0002
B0
Y0
A0
0
3
1
1
1
0