dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 296

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Instruction Pipeline
10.3.7
Figure 10-7 on page 10-17 shows the fast interrupt pipeline for the case of a short, three-instruction, fast
interrupt service routine where the following occur:
The point at which interrupts are re-enabled after the exception processing state is exited is shown in the
interrupt pipeline in Figure 10-7. Interrupt arbitration begins again in cycle #11. Even if a level 3 priority
interrupt is received, it is not sampled by the interrupt arbiter until instruction cycle #11, as the figure
shows. This arrangement allows a minimum of 5 clock cycles in the fast interrupt routine to be executed
without being interrupted.
For this short, 3-word interrupt service routine, the fast interrupt routine completes and control returns to
the main program before the second interrupt request is serviced. All interrupt priority levels are eligible
already by cycle #11 because, by this time, the FRTID instruction has restored the status register to its
original value.
In Figure 10-7 on page 10-17, the second interrupt is level 0, 1, or 2. In this case, the interrupt will be
successfully arbitrated in cycle #12 after the contents of the status register have been restored by the
FRTID instruction in cycle #11. This allows a minimum of 2 instruction cycles from the main program to
be executed before the second interrupt is serviced. Additional cycles will be executed if n2 is more than 2
cycles or if n3 is a multi-cycle instruction.
Consider a second case, slightly different from the one shown in Figure 10-7, in which the second interrupt
is level 3. In this case, the interrupt will be successfully arbitrated in cycle #11; exactly one instruction
from the main program will be executed before the second interrupt is serviced.
10-16
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A fast interrupt request is received.
Simultaneously with this request or a short time after it is received, a second interrupt is received.
FIRQ Followed by Another Interrupt
DSP56800E Core Reference Manual
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