dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 250

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Program Controller
when LC is loaded with a loop count before DOSLC is executed. When a DO or DOSLC loop terminates,
the value in the LC2 register is copied back into the LC register when the OMR's NL bit is set. See
Section 8.5, “Hardware Looping,” for a full discussion hardware looping.
LC2 may be pushed onto or popped from the software stack under program control. This capability allows
an application to save and restore this register when necessary.
8.2.5
The loop address (LA) register holds the location of the last instruction word in a hardware DO loop, and it
is used by the looping hardware to determine when the end of a loop has been reached.
The value in the LA register is set when the DO instruction is executed, and it may also be updated when a
DO loop that is nested in another DO loop is exited, at which point the contents of LA2 are copied to it.
The LA register can be read or written using a MOVE instruction. When the register is read as a 32-bit
long with a MOVE.L instruction, the upper 8 bits of the destination are zero extended. When it is written as
a 32-bit long by a MOVE.L instruction, only the lower 24 bits are stored in LA.
8.2.6
The loop address 2 register (LA2) is a 24-bit register that is used to save the value of LA when a DO loop
that is nested within another DO loop is executed. When a DO or DOSLC instruction is executed, the
contents of LA are copied to LA2 before the end-of-loop address for the inner loop is stored in LA. When
the nested loop terminates, the value in LA2 is copied back to LA to allow the outer loop to continue. See
Section 8.5, “Hardware Looping,” for more information on nested hardware loops.
LA2 may be read from and written to the stack under program control. This capability allows an
application to save and restore this register when necessary.
8.2.7
The hardware stack register (HWS) is used to manipulate the program controller’s hardware stack under
program control. Accesses to HWS always read or write the value on the top of the stack; the second stack
location is not directly accessible. Reading from or writing to HWS can affect the LF bit in the status
register and the NL bit in the operating mode register. See Section 8.4, “Hardware Stack,” for more
information.
The HWS register is accessed with standard MOVE instructions. When the register is read as a 32-bit long
by a MOVE.L instruction, the upper 8 bits of the destination register are zero extended. When it is written
as a 32-bit long by a MOVE.L instruction, only the lower 24 bits are stored on the hardware stack.
8.2.8
The fast interrupt status register (FISR) is a 13-bit register that is used to hold the state of the DSP56800E
core during fast interrupt processing. Critical bits in the status register (SR) and operating mode register
(OMR), as well as the alignment of the stack pointer, are copied into the FISR at the beginning of fast
interrupt processing. The value in the FISR is used to restore the core state when a fast interrupt processing
routine is exited.
8-12
Loop Address Register
Loop Address Register 2
Hardware Stack Register
Fast Interrupt Status Register
DSP56800E Core Reference Manual
Freescale Semiconductor