dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 493

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

IMPYSU
Operation:
S1 × S2 → D
Description: Multiply one signed 16-bit source operand by one unsigned 16-bit operand, and place the 32-bit integer
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Instruction Fields:
Instruction Opcodes:
Timing:
Memory:
Freescale Semiconductor
Operation
IMPYSU q1.h,q2.l,Y
IMPYSU
Before Execution
B2
A2
0
0
product in the destination (D). The order of the registers is important. The first source register (S1)
must contain the signed value, and the second source (S2) must contain the unsigned value to produce
the correct integer multiplication. The destination for this instruction is always the Y register. The re-
sult is not affected by the state of the saturation bit (SA).
This instruction is used to perform extended-precision multiplication calculations. It provides a meth-
od for calculating one of the intermediate values that is needed when a 32-bit × 32-bit multiplication
is performed, for example. See Section 5.5.3, “Multi-Precision Integer Multiplication,” on page 5-32
for an example that uses the IMPYSU instruction.
IMPYSU A1,B0,Y
Prior to execution, the A accumulator contains the value $0:FFFE:1234, the B accumulator contains
$0:0000:0002, and the 32-bit Y register contains $1234:5678. Execution of the IMPYSU instruction
multiplies the 16-bit (signed) negative value in A1 by the 16-bit (unsigned) positive value in B0 and
stores the (signed) negative result ($FFFF:FFFC) into Y.
The condition codes are not modified by this instruction.
1 oscillator clock cycle
1 program word
A1,C0,Y
A1,D0,Y
A1,A0,Y
A1,B0,Y
(S1 signed; S2 unsigned)
FFFE
0000
1234
B1
A1
Y1
Integer Multiply Signed and Unsigned
Operands
0002
1234
5678
C1,C0,Y
C1,D0,Y
B1,C0,Y
B1,D0,Y
B0
A0
Y0
15
0
Instruction Set Details
1
; multiply signed A1 to unsigned B0, store in Y
1
Assembler Syntax:
IMPYSU
12
C
1
1
11
0
W
1
After Execution
0
B2
A2
Integer 16 × 16 multiply:
F1 (signed) × F0 (unsigned)
0
0
1
S1,S2,D
0
8
FFFE
FFFF
0000
B1
Y1
A1
7
0
q
Comments
q
(no parallel move)
q
4
IMPYSU
FFFC
0002
1234
B0
Y0
A0
0
3
1
1
A-149
1
0