dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 589

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

RND
Operation:
D + r →
D + r →
Description: Round the 36-bit or 32-bit value in the specified destination operand (D). If the destination is an accu-
Example:
Explanation of Example:
Condition Codes Affected:
Freescale Semiconductor
I
II
III
Before Execution (R = 0; convergent)
Before Execution (R = 0; convergent)
Before Execution (R = 1; two’s-complement)
A2
A2
A2
D
D
0
0
0
mulator, store the result in the EXT:MSP portions of the accumulator and clear the LSP. When the des-
tination is the 32-bit Y register, store the result in Y1 and clear Y0. This instruction uses the rounding
technique that is selected by the R bit in the OMR. When the R bit is cleared (default mode), conver-
gent rounding is selected; when the R bit is set, two’s-complement rounding is selected. Refer to
Section 5.9, “Rounding,” on page 5-43 for more information about the rounding modes.
RND
Prior to execution, the 36-bit A accumulator contains the value $0:1234:789A for case I and the value
$0:1234:8000 for case II and case III. Execution of the RND instruction rounds the value in the A ac-
cumulator into the MSP of the A accumulator (A1) and then zeros the LSP of the A accumulator (A0).
Case I assumes that convergent rounding is selected. Case II and case III demonstrate convergent
rounding versus two’s-complement rounding by applying them to the same initial value. The only con-
dition under which these algorithms generated different results is when A1 is even and A0 contains the
boundary value $8000.
SZ — Set according to the standard definition of the SZ bit (parallel move)
L
E
U
N
Z
V
LF
15
— Set if overflow has occurred in result
— Set if the extended portion of result is in use
— Set according to the standard definition of the U bit
— Set if MSB of result is set
— Set if result equals zero
— Set if overflow has occurred in result
(one parallel move)
(no parallel move)
P4
14
1234
1234
1234
A1
A1
A1
A
13
P3
P2
12
MR
P1
11
; round A accumulator into A2:A1, zero A0
789A
8000
8000
P0
10
A0
A0
A0
Instruction Set Details
I1
9
Round
Assembler Syntax:
RND
RND
I0
8
SZ
7
After Execution
After Execution
After Execution
6
L
A2
A2
A2
0
0
0
5
E
D
D
U
4
CCR
1234
1234
1235
N
3
A1
A1
A1
(one parallel move)
(no parallel move)
2
Z
V
1
C
0
0000
0000
0000
A0
A0
A0
RND
A-245