dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 185

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

In the CMP.B, CMP.BP, and CMP.W instructions, condition codes are based on 8- or 16-bit results, with
corresponding 8- or 16-bit source operands. The CMP.L and CMP instructions generate condition codes on
32- and 36-bit results, respectively, but one of the two operands can be a 16-bit word. In each case,
condition codes are calculated based on the size that is specified in or implied by the instruction opcode.
5.8
DSC algorithms can generate values that are larger than the data precision of the machine when real data
streams are processed. Normally a processor simply overflows its result when this generation occurs, but
overflow creates problems for processing real-time signals. The solution is saturation, or data limiting,
which guarantees that values are always within a given range.
Saturation is especially important when data is run through a digital filter whose output goes to a
digital-to-analog converter (DAC), since saturation “clips” the output data instead of allowing arithmetic
overflow. Without saturation, the output data could incorrectly switch from a large positive number to a
large negative value, which would almost certainly cause unwanted results.
As an alternative to overflow, the DSP56800E provides optional saturation of results through two limiters
that are within the data ALU. The data limiter saturates values when moving data out of an accumulator
with a move instruction or parallel move. The MAC output limiter limits the output of the data ALU’s
MAC unit.
5.8.1
The data limiter protects against overflow by selectively limiting when an accumulator register is read as a
source operand in a move instruction. Test logic in the extension portion of each accumulator register
detects overflows so that the limiter can substitute one of two constants to minimize errors that are due to
overflow. This process is called “saturation arithmetic.” When limiting occurs, a flag is set and latched in
the status register. The value of the accumulator is not changed.
When a MOVE.W instruction specifies an accumulator (FF) as a source, and when the contents of the
selected source accumulator can be represented in the destination operand size without overflow (that is,
the accumulator extension register is not in use), the data limiter does not saturate and the register contents
are stored unmodified. If a MOVE.W instruction is used and the contents of the selected source
accumulator cannot be represented in the destination operand size without overflow, the data limiter places
a “limited” data value in the destination that has maximum magnitude and the same sign as the source
accumulator. Table 5-3 summarizes these scenarios. The value in the accumulator is not changed.
Although the following examples all involve fractional data and arithmetic, saturation is equally applicable
to integer arithmetic.
Freescale Semiconductor
Extension Bits in Use in Selected
Saturation and Data Limiting
Data Limiter
Accumulator?
Yes
Yes
No
Table 5-3. Data Limiter Saturation
Data Arithmetic Logic Unit
MSB of FF2
(Don’t care)
0
1
Same as input—unmodified MSP
$7FFF—maximum positive value
$8000—maximum negative value
Output of Limiter onto the CDBW Bus
Saturation and Data Limiting
5-39