dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 199

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

6.2.3
The N register is one of the most powerful registers in the AGU. In addition to functioning as an address
pointer similar to the R0–R5 registers, it can also be used for indexed and post-update addressing modes.
When the N register is used as an offset for post-updating, its value is truncated to 16 bits and then sign
extended to 24 bits before being passed to the primary arithmetic unit for post-updating. When the N
register is used as an offset for accessing long memory locations, its value is shifted to the left by 1 bit
before it is passed to the primary arithmetic unit for calculating the effective address. Thus, in this case, the
N offset is a long offset.
6.2.4
The secondary read offset register (N3) is a 16-bit register that is used for post-updating the R3 pointer
register in dual read instructions, which read two values from data memory. The N3 register is sign
extended to 24 bits and passed to the secondary address adder unit for post-updating the R3 pointer
register.
6.2.5
The modifier register (M01) specifies whether linear or modulo arithmetic is used when a new address is
calculated. This modifier register is automatically read when the R0 or R1 address register is used in an
address calculation. This register has no effect on address calculations done with the R2–R5, N, or SP
registers.
During processor reset this register is set to $FFFF, which enables linear arithmetic for the R0 and R1
registers. Programming the modifier register is discussed in Section 6.8.3, “Configuring Modulo
Arithmetic.”
6.2.6
The DSP56800E provides four shadow registers corresponding to the R0, R1, N, and M01 address
registers. The shadow registers are not directly accessible, but become available when their contents are
swapped with the contents of the corresponding AGU core registers. This swapping is accomplished
through executing the
their shadowed counterparts. When the original values of the registers are required, executing the
SWAP SHADOWS
Using shadow registers as dedicated address registers during fast interrupt processing can greatly reduce
the considerable overhead incurred by saving and restoring registers when exception handlers are entered
and exited. Fast interrupts are described in Section 9.3.2.2, “Fast Interrupt Processing,” on page 9-6. The
SWAP instruction enables the shadow registers to be used to minimize the overhead during normal
interrupt processing.
Freescale Semiconductor
Offset Register (N)
Secondary Read Offset Register (N3)
Modifier Register (M01)
Shadow Registers
The M01 register should never be used for general-purpose storage
because its value affects calculations with the R0 and R1 pointers.
The shadow register corresponding to M01 is not initialized by the
DSP56800E core at reset. It must be explicitly programmed by the user.
instruction a second time restores the original values.
SWAP SHADOWS
Address Generation Unit
instruction. The contents of the four registers are exchanged with
NOTE:
NOTE:
AGU Programming Model
6-5