dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 578

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

NORM
Operation:
If (E • U • Z = 1) then
else if (E = 1) then
else
where X denotes the logical complement of X, and • denotes the logical AND operator
Description: Perform one normalization iteration on the specified destination operand (D), update the address reg-
Example:
Explanation of Example:
A-234
Before Execution
A2
ASL D and Rn – 1 → Rn
0
ASR D and Rn + 1→ Rn
NOP
ister R0 based upon the results of that iteration, and store the result back in the destination accumulator.
This is a 36-bit operation. If the accumulator extension is not in use, the accumulator is unnormalized,
and if the accumulator is not zero, then the destination operand is arithmetically shifted 1 bit to the left,
and the specified address register is decremented by one. If the accumulator extension register is in use,
the destination operand is arithmetically shifted 1 bit to the right, and the specified address register is
incremented by 1. If the accumulator is normalized or zero, a NOP is executed, and the specified ad-
dress register is not affected. Since the operation of the NORM instruction depends on the CCR bits
E, U, and Z, these bits must correctly reflect the current state of the destination accumulator prior to
the execution of the NORM instruction. The L and V bits in the CCR will be cleared unless they have
been improperly set up prior to the execution of the NORM instruction.
TST
REP
NORM
Prior to execution, the 36-bit A accumulator contains the value $0:0000:8000, and the R0 address reg-
ister contains the value $000000. The repetition of the NORM instruction normalizes the value in the
36-bit accumulator and stores the resulting number of shifts that are performed during that normaliza-
tion process in the R0 address register. A negative value reflects the number of left shifts performed
during the normalization process, while a positive value reflects the number of right shifts performed.
In this example, 15 left shifts are required for normalization.
R0
0000
A1
A
#31
R0,A
SR
Normalize Accumulator Iteration
000000
DSP56800E Core Reference Manual
8000
0310
A0
;establish condition codes for NORM
;maximum number of iterations (31) needed
;perform one normalization iteration
Assembler Syntax:
(after TSTA)
After Execution
A2
0
NORM
R0
4000
A1
SR
R0,D(no parallel move)
FFFFF1
Freescale Semiconductor
0000
0300
A0
NORM