dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 284

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Instruction Pipeline
The abbreviations n1 and n2 refer to the first and second instructions, respectively, that are executed in the
pipeline. The fourth instruction, n4, contains an instruction extension word (typically an absolute address
or immediate value), which is labeled n4e. As shown in Table 10-2, it takes an additional clock cycle to
fetch and process the extension word.
All instructions are referred to by their n abbreviations before they reach the Instruction Decode stage of
the pipeline. Then, as Table 10-2 demonstrates, the instructions are referred to by name (or by a shortened
version thereof) to reflect that they have been identified.
It can be seen that although each instruction takes many clock cycles to complete execution, throughput
remains high due to the pipelining.
10.2.2
Data ALU instructions are executed in the last two stages of the pipeline, Execute and Execute 2. Data
ALU instructions execute in one of four ways:
10-4
P1 (Pre-Fetch 1)
P2 (Pre-Fetch 2)
IF (Instruction Fetch)
ID (Instruction Decode)
AG (Address Generation)
OP2 (Operand Pre-Fetch 2)
EX (Execute and Operand Fetch)
EX2 (Execute 2)
1.In all of the pipeline tables in this chapter, MOVE instructions are notated as “mov.”
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Normal Execution—Arithmetic and logical instructions that begin and complete execution in the
Execute phase.
Late Execution—Arithmetic and logical instructions that begin and complete execution in the
Execute 2 phase.
Two-Stage Execution—Multiplication, multiply-accumulate, and multi-bit shifting instructions
that begin execution in the Execute phase and complete in the Execute 2 phase. These instructions
place the data ALU into Late mode.
Multi-Cycle Execution—Data ALU instructions that execute in more than 1 clock cycle.
Pipeline Stage
Data ALU Execution Stages
MOVE.W
ADD
MOVE.W
MOVE.W
INC.W
Example 10-1. Example Code to Demonstrate Pipeline Flow
X:(R0),A
A,B
B,C
C1,X:$0C00
C
n1
DSP56800E Core Reference Manual
1
Table 10-2. Instruction Pipelining
n2
n1
2
n3
n2
n1
3
; n1: 1-word, 1-cycle instruction
; n2: 1-word, 1-cycle instruction
; n3: 1-word, 1-cycle instruction
; n4: 2-word, 2-cycle instruction
; n5: 1-word, 1-cycle instruction
mov
n4
n3
n2
4
1
mov
n4e
add
n4
n3
5
Instruction Cycle
mov
mov
n4e
add
n5
n4
6
mov
mov
mov
n4e
add
n5
7
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mov
mov
mov
add
n5
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Freescale Semiconductor
mov
mov
mov
inc
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mov
mov
inc
10
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mov
inc
11
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