dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 655

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dsp56800e

Manufacturer Part Number
dsp56800e
Description
16-bit Digital Signal Controller Core
Manufacturer
Freescale Semiconductor, Inc
Datasheet
ZXT.B
Operation:
0 → D[MSB:8]
S[7:0] → D[7:0]
Description: Zero extend a byte that is located in the source register, and place the extended value into the destina-
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Instruction Fields:
Instruction Opcodes:
Timing:
Memory:
Freescale Semiconductor
ZXT.B
Operation
ZXT.B
Before Execution
FFF,FFF
A2
C
X0
tion (D). If the destination register is an accumulator, the value is aligned such that the original byte
value is located in the low-order 8 bits of the MSP of the destination accumulator (or Y register). If the
source is a 16-bit register, it is internally concatenated with 16 zero bits to form a 32-bit value. The
upper 8 bits of this value corresponds to the zero extension from bit 24 and then moved to the destina-
tion. If the destination is a 16-bit register, only the upper 16 bits of this value are stored. The result is
not affected by the state of the saturation bit (SA).
ZXT.B can be used to zero extend a 24-bit value into an accumulator by using the Y register as the
source for the operation.
ZXT.B
Initially, the A accumulator holds the value $C:26A7:1A36, and the X0 register holds $81F3. The byte
in X0 is zero extended to form the 32-bit value $00F3:0000 and stored in the A accumulator (with
4 bits of zero extension).
The condition codes are not affected by this instruction.
1 oscillator clock cycle
1 program word
(no parallel move)
26A7
81F3
A1
X0,A
Operands
FFF,FFF
FFF
1A36
A0
15
Zero Extend Byte
0
Instruction Set Details
1
; zero extend byte in X0 and place in A
C
1
1
1
Assembler Syntax:
ZXT.B
W
12
1
1
1
Zero extend byte. When the destination is the Y regis-
ter or an accumulator, the LSP portion is cleared if the
source is a 16-bit register.
An alternate syntax for the preceding instruction if the
source and the destination are the same.
11
1
After Execution
A2
0
X0
1
F
S,D
F
00F3
81F3
8
A1
F
7
(no parallel move)
Comments
b
b
b
0000
4
A0
0
3
ZXT.B
0
1
A-311
0
0

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