dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 343

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

When the core_tap_en pin is deasserted the TAP controller returns to the Run-Test/Idle state at the next
rising edge of TCK and remains there until the TAP is re-enabled to follow the transitions and state of the
TMS signal, by core_tap_en pin assertion.
There are two paths through the 16-state machine. The Shift-IR_Scan path is used to capture and load core
JTAG instructions into the core JTAG IR. The Shift-DR_Scan path captures and loads data into the other
core JTAG registers. The core TAP controller executes the last instruction decoded until a new instruction
is entered at the Update-IR state or until the Test-Logic-Reset state is entered. When using the core JTAG
port to access EOnCE module registers, accesses are first enabled by shifting the ENABLE_EOnCE
instruction into the core JTAG IR. After this is selected, the EOnCE module registers and commands are
read and written through the core JTAG pins using the Shift-DR_Scan path. Asserting the tlm_reset_b pin
low asynchronously forces the core JTAG state machine into the Test-Logic-Reset state.
Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE)
1
0
Test-Logic-Reset
Run-Test/Idle
0
Figure 11-17. TAP Controller State Diagram
1
0
1
Select-DR-Scan
Capture-DR
Pause-DR
Update-DR
Exit1-DR
Shift-DR
Exit2-DR
1
0
1
1
0
1
0
0
1
1
0
0
0
1
Select-IR-Scan
Capture-IR
Update-IR
Pause-IR
Shift-IR
Exit1-IR
1
Exit2-IR
0
1
1
0
1
0
0
JTAG Port
1
0
1
0
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