dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 201

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

6.4
As discussed in Section 3.5.1, “Word and Byte Pointers,” on page 3-17, the DSP56800E supports two
types of addresses for data memory accesses: word and byte. Depending on the type of address used, the
memory map is interpreted somewhat differently. Figure 6-4 on page 6-8 shows the differences between
the memory maps.
Freescale Semiconductor
Register
Pointer
R4
R5
SP
N
Byte and Word Addresses
(Rn)
(Rn)+
(Rn)–
(Rn)+N
(Rn+N)
(RRR+x)
(Rn+xxxx)
(Rn+xxxxxx)
(Rn)
(Rn)+
(Rn)–
(Rn)+N
(Rn+N)
(RRR+x)
(Rn+xxxx)
(Rn+xxxxxx)
(Rn)
(Rn)+
(Rn)–
(Rn)+N
(Rn+N)
(RRR+x)
(Rn+xxxx)
(Rn+xxxxxx)
(Rn)+
(Rn)–
(Rn)+N
(Rn+N)
(SP–x)
(SP–xx)
(Rn+xxxx)
(Rn+xxxxxx)
(Rn)
Addressing
Allowed
Modes
Table 6-1. Capabilities of the Address Pointer Registers (Continued)
Allowed?
Modulo
No
No
No
No
Pointer for primary access in dual read instructions
Available not only as a pointer register, but also as indexing and post-update
register.
Shadowed for use with fast interrupt processing.
Supports 1-word indexed addressing with 6-bit offset for word moves.
Used implicitly by the JSR, RTS, RTSD, RTI, RTID and FRTID instructions.
SP is always used as a word pointer to properly support stack operations.
Supports legacy addressing mode (SP+N).
Address Generation Unit
Capabilities and Notes
Byte and Word Addresses
6-7