dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 354

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

ADC
Operation:
S + C + D → D
Description: Add the source operand (S) and the carry bit (C) to the second operand, and store the result in the des-
Usage:
Example:
Explanation of Example:
Note:
Condition Codes Affected:
A-10
Before Execution
A2
0
tination (D). The source operand (register Y) is first sign extended internally to form a 36-bit value
before being added to the destination accumulator. The result is not affected by the state of the satura-
tion bit (SA).
This instruction is typically used in multi-precision addition operations (see Section 5.5.1, “Extend-
ed-Precision Addition and Subtraction,” on page 5-29) when it is necessary to add together two num-
bers that are larger than 32 bits (as in 64-bit or 96-bit addition).
ADC
Prior to execution, the 32-bit Y register—which is composed of the Y1 and Y0 registers—contains the
value $2000:8000, and the 36-bit accumulator contains the value $0:2000:8000. In addition, the initial
value of C is set to one. The ADC instruction automatically sign extends the 32-bit Y register to 36 bits
and adds this value to the 36-bit accumulator. The carry bit, C, is added into the LSB of this 36-bit
operation. The 36-bit result is stored back in the A accumulator, and the condition codes are set appro-
priately. The Y1:Y0 register pair is not affected by this instruction.
C is set correctly for multi-precision arithmetic, using long-word operands only when the extension
register of the destination accumulator (FF2) contains only sign extension information (bits 31 through
35 are identical in the destination accumulator).
L
E
U
N
Z
V
C
LF
15
— Set if overflow has occurred in result
— Set if the extended portion of accumulator result is in use
— Set according to the standard definition of the U bit
— Set if bit 35 of accumulator result is set
— Set if accumulator result is zero; cleared otherwise
— Set if overflow has occurred in accumulator result
— Set if a carry (or borrow) occurs from bit 35 of accumulator result
(no parallel move)
2000
2000
P4
14
A1
Y1
Y,A
13
P3
SR
P2
12
MR
DSP56800E Core Reference Manual
P1
11
Add Long with Carry
8000
8000
0301
A0
Y0
P0
10
; add Y and carry to A
I1
9
Assembler Syntax:
ADC
I0
8
SZ
7
After Execution
6
L
A2
0
5
E
S,D
U
4
CCR
4001
2000
A1
Y1
N
3
(no parallel move)
SR
2
Z
Freescale Semiconductor
V
1
0001
8000
0300
C
0
A0
Y0
ADC