dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 485

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

IMAC.L
Operation:
D + (S1 × S2) → D
Description: Multiply the two signed 16-bit source operands, and add the 32-bit integer product to the destination
Example:
Explanation of Example:
Condition Codes Affected:
Freescale Semiconductor
Before Execution
B2
A2
0
0
(D). Both source operands must be located in the FF1 portion of an accumulator. The destination for
this instruction can be an accumulator or the Y register. If an accumulator is used as the destination,
the product is first sign extended from bit 31 and a 36-bit addition is then performed. The result is not
affected by the state of the saturation bit (SA).
IMAC.L A1,B1,Y
Prior to execution, the A accumulator contains the value $0:0002:FFFF, the B accumulator contains
$0:0004:1234, and the 32-bit Y register contains $0000:0002. Execution of the IMAC.L instruction
multiplies the 16-bit signed value in A1 by the 16-bit signed value in B1, adds the resulting sign-ex-
tended product to the 32-bit Y register, and stores the 32-bit signed result ($0000:000A) into Y.
L
E
U
N
Z
V
Condition codes are calculated based on the 36-bit result if the destination is an accumulator, and on
the 32-bit result if the destination is the Y register.
LF
15
— Set if overflow has occurred in result
— Set if the extension portion of the result is in use
— Set if the result is unnormalized
— Set if bit 35 (or 31) of the result is set
— Set if the result is zero
— Set if overflow has occurred in result
(no parallel move)
0004
0000
0002
P4
14
B1
Y1
A1
Integer Multiply with Accumulate Long
13
P3
SR
P2
12
MR
P1
11
FFFF
1234
0002
0300
B0
Y0
A0
P0
10
Instruction Set Details
I1
9
Assembler Syntax:
IMAC.L
I0
8
SZ
7
After Execution
6
L
B2
A2
0
0
5
E
S1,S2,D
U
4
CCR
0004
0000
0002
B1
Y1
A1
N
3
2
Z
SR
V
(no parallel move)
1
C
0
FFFF
000A
1234
0310
IMAC.L
B0
Y0
A0
A-141