dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 287

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

10.3
The instruction pipeline functions slightly differently when processing interrupt requests. Beyond the
standard eight-stage pipeline, additional cycles are required for arbitrating and interrupting the core. On a
typical chip implementation, two extra stages are required. This addition effectively makes the interrupt
pipeline 10 levels deep. The two additional stages are as follows:
The Interrupt Arbitration stage is required for arbitrating among all the different possible requesting
sources. If a valid interrupt is found at a high enough priority level after this arbitration is performed, the
program interrupt controller asserts an interrupt request to the core. This assertion occurs during the
Interrupt Request stage.
Note in this example that these 2 additional processing cycles are not real stages in the pipeline. Rather,
they are performed in the interrupt controller, and they do not directly affect the operation of the pipeline.
However, these cycles do affect the overall processing time for an interrupt, so they can be considered
additional pipeline stages for the purpose of calculating interrupt latency. For an exact calculation of
interrupt latency, refer to Section 10.3.8, “Interrupt Latency.”
10.3.1
Figure 10-2 on page 10-8 shows the program flow and pipeline during standard interrupt processing.
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Interrupt Arbitration (Int Arbitr)
Interrupt Request (Int Req)
Pipeline During Interrupt Processing
Standard Interrupt Processing Pipeline
Instruction Pipeline
Pipeline During Interrupt Processing
10-7