dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 196

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Address Generation Unit
Figure 6-2 illustrates a dual parallel read instruction, which uses 1 program word and executes in
1 instruction cycle. The primary operand is addressed with XAB1, and the second operand is addressed
with XAB2. The data memory, in turn, places its data on the core data bus for reads (CDBR) and on the
second data bus (XDB2), respectively. See Section 3.3.5, “Parallel Moves,” on page 3-11 for more
discussion of parallel memory moves.
The AGU can directly address 2
program memory. All three buses can generate addresses to on-chip or off-chip memory.
6.1.1
The primary address arithmetic unit is used when AGU arithmetic instructions are performed and when
complex operand effective addresses are calculated, as in indexing and post-updating. Byte, word, and
long-word accesses are supported.
6-2
Immediate Data
15
Short or Long
Primary Address Arithmetic Unit
Registers
Modifier
M01
MOVE.W
Arithmetic
Primary
pass, <<1
Unit
0
Figure 6-1. Address Generation Unit Block Diagram
Figure 6-2. Dual Parallel Read Instruction
24
DSP56800E Core Reference Manual
(16,777,217) locations in data memory and 2
23
PAB
(Uses XAB1 and CDBR)
X:(R4)+N,Y0
Primary Read
Pointer Registers
Byte Select
pass, >>1
CDBW
CDBR
R0
R1
R2
R3
R4
R5
N
SP
(Uses XAB2 and XDB2)
XAB1
X:(R3)+N3,X0
Secondary Read
0
R3 Only
R3
To
XAB2
Secondary
21
Adder
15
Freescale Semiconductor
(2,097,152) locations in
Secondary
Register
Offset
N3
0