dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 344
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dsp56800e
Manufacturer Part Number
dsp56800e
Description
16-bit Digital Signal Controller Core
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56800E.pdf
(706 pages)
- Current page: 344 of 706
- Download datasheet (4Mb)
JTAG and Enhanced On-Chip Emulation (Enhanced OnCE)
11.5.3
JTAG Port Restriction — STOP Processing State
The core features a low-power stop mode, that is invoked by the Hawk V2 core executing a STOP
instruction. Since all Hawk V2 core clocks are disabled during Stop mode, the JTAG interface provides the
means of polling the device status (sampled in the capture-IR state). The core JTAG TAP will bring the
core out of Stop or Wait modes when DEBUG_REQUEST is decoded in the TAP IR. A small amount of
additional power above the minimum possible will be expended by the core TAP logic if the core TAP is
utilized during Stop mode.
11-32
DSP56800E Core Reference Manual
Freescale Semiconductor
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