dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 212

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Address Generation Unit
6.7
In addition to the address arithmetic performed by the various addressing modes, the AGU supports a
number of powerful instructions for directly manipulating address registers. The AGU arithmetic
instructions enable more complex address calculations. These instructions make no distinction between
word and byte pointers, calculating results the same way for both.
Table 6-5 summarizes the AGU arithmetic instructions. For more detailed information, refer to the
appropriate entry in Appendix A, “Instruction Set Details.”
6-18
ADDA Rm,Rn
ADDA.L Rm,Rn
ADDA Rm,Rn,N
ADDA.L Rm,Rn,N
ADDA #x,Rn
ADDA #x,Rn,N
ADDA #xxxx,Rm,Rn
ADDA.L #xxxx,Rm,Rn
ADDA #xxxx,HHH,Rn
ADDA.L #xxxx,HHH,Rn
ADDA #xxxxxx,Rm,Rn
ADDA.L #xxxxxx,Rm,Rn
ADDA #xxxxxx,HHH,Rn
ADDA.L #xxxxxx,HHH,Rn
ASLA Rm,Rn
ASRA Rn
CMPA Rm,Rn
CMPA.W Rm,Rn
DECTSTA Rn
AGU Arithmetic Instructions
Instruction
Table 6-5. AGU Address Arithmetic Instructions
DSP56800E Core Reference Manual
Rn = Rn+Rm
Rn = Rn+(Rm<<1)
N = Rn+Rm
N = Rn+(Rm<<1)
Rn = #x+Rn
N = #x+Rn
Rn = #xxxx+Rm
Rn = #xxxx+(Rm<<1)
Rn = #xxxx+HHH
Rn = #xxxx+(HHH<<1)
Rn = #xxxxxx+Rm
Rn = #xxxxxx+(Rm<<1)
Rn = #xxxxxx+HHH
Rn = #xxxxxx+(HHH<<1)
Rn = (Rm<<1)
Rn = (Rn>>1)
Rn–Rm
Rn–Rm
Rn = Rn–1
Address Calculation
#x is a 4-bit unsigned value.
#x is a 4-bit unsigned value.
#xxxx is a signed 17-bit value.
#xxxx is an unsigned 16-bit value.
HHH—data ALU register that is treated as a
signed 16-bit value.
#xxxx is an unsigned 16-bit value.
HHH—data ALU register that is treated as a
signed 16-bit value.
#xxxx is an unsigned 16-bit value.
#xxxxxx is a signed 24-bit value.
#xxxxxx is a signed 24-bit value.
HHH—data ALU register that is treated as a
signed 16-bit value.
#xxxx is an unsigned 16-bit value.
HHH—data ALU register that is treated as a
signed 16-bit value.
#xxxx is an unsigned 16-bit value.
Arithmetic right shift.
The result is not stored, but the condition codes
are set based on the 24-bit result.
The result is not stored, but the condition codes
are set based on the lowest 16 bits of the result.
Decrement by one and then set the condition
codes.
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