dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 245

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

8.2.1.7
The condition code mode (CM) bit selects whether condition codes are calculated with 36-bit or 32-bit data
ALU results. When this bit is set, the C, N, V, and Z condition codes are calculated based on 32-bit results.
When this bit is cleared, these condition codes are generated based on 36-bit results. See Section B.1.3,
“Condition Code Mode,” on page B-3 for a more detailed description of the effect of the CM bit on the
condition codes. This bit is cleared by processor reset.
In general, programs should not set the CM bit unless it is required for compatibility with the DSP56800
architecture. The DSP56800E instruction set contains test and compare instructions for byte, word,
long-word, and 36-bit values in the accumulators, obviating the need for the CM bit functionality.
8.2.1.8
The nested looping (NL) bit reflects the status of hardware DO loops and the hardware stack. If this bit is
set, then the program is currently executing a DO loop that is nested inside another DO loop. If this bit is
clear, a nested DO loop is not being executed. This bit is used by the looping hardware to correctly save
and restore the contents of the hardware stack. REP looping does not affect this bit.
The NL bit is also affected by any direct accesses to the hardware stack register. See Section 8.4,
“Hardware Stack,” for a more detailed discussion. The NL bit is cleared on processor reset.
8.2.2
The status register (SR) is a 16-bit register that consists of an 8-bit mode register (MR) and an 8-bit
condition code register (CCR). MR occupies the high-order 8 bits of the SR; CCR occupies the low-order
8 bits.
The mode register reflects and defines the operating state of the DSC core, including the current interrupt
priority level. The condition code register reflects various properties of the values that result from
instruction execution.
Freescale Semiconductor
Status Register
Condition Code Mode (CM)—Bit 8
Nested Looping (NL)—Bit 15
The CM bit on the DSP56800E architecture is identical in function to the
DSP56800’s CC bit. The bit has been renamed for the DSP56800E in the
interest of clarity.
Program Controller
NOTE:
Program Controller Programming Model
8-7