dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 277

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

effectively disabled until after the last instruction in the sequence. In the following sets of instructions,
interrupts cannot occur between the instructions:
Consider the code fragment in Example 9-1. BRSET is an instruction that causes interrupts to be
temporarily disabled, as noted in the preceding list.
LABEL
If the branch is not taken, interrupts will be disabled until after the DEC.W instruction is executed. Any
interrupts that occur during the time that is taken to execute these three instructions will be deferred until
the end of this sequence. If the branch is taken, interrupts can occur between the BRSET and ADD
instructions.
The SWI instruction is included in this list because of the nature of this instruction. The SWI instruction is
designed so that upon execution, the instruction immediately after the SWI will not be executed; instead,
the processor directly enters the exception processing state. Thus, by design, no interrupts can occur
between the execution of the SWI instruction and the processor’s direct entry into the exception processing
state.
9.4
One of the DSP56800E core’s low-power-consumption states is wait mode. This mode is entered by
executing the WAIT instruction. After a delay, the processor enters a state where the internal clock to the
core is disabled and clocks to the memories are typically disabled, but where clocks continue to run to the
on-chip peripherals and to the interrupt controller.
Freescale Semiconductor
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A delayed flow control instruction (such as JMPD) and the instructions in the delay slots
A REP instruction and the instruction that is to be repeated
A 1-word Bcc instruction and either of the following:
— A multi-word instruction
— A 1-word instruction and the instruction that immediately follows it
A multi-word Bcc and the instruction immediately after the Bcc
BRSET or BRCLR and either of the following:
— A multi-word instruction
— A 1-word instruction and the instruction that immediately follows it
A Jcc instruction and the instruction that is executed immediately after the Jcc
A Tcc instruction with an
An
An SWI at the highest priority level and the instruction that immediately follows it (see following
paragraph on SWI)
Any of the last 3 program words in a hardware DO or DOSLC loop during the last iteration of the
hardware loop
Wait Processing State
ADD.W X:(SP-xx),EEE
NOP
BRSET
ASL
DEC.W
MOVE.W
ADD
#34,X0,LABEL
A
X:$3400
Y0,X0
X0,A
Example 9-1. BRSET Non-Interruptible Sequence
R0,R1
instruction and the instruction that immediately follows it
register transfer and the instruction that immediately follows it
Processing States
; (interrupt may occur before BRSET)
; Begins Non-Interruptible Sequence
; ===> No interrupt allowed before ASL
; ===> No interrupt allowed before DEC
; (interrupt allowed before MOVE)
; (interrupt allowed if branch taken)
Wait Processing State
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