dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 310

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Instruction Pipeline
10.4.3
There is an infrequently used class of move instructions that introduce stalls into the pipeline due to
pipeline effects. The assembler will issue a warning when any of these instructions are encountered.
The pipeline automatically inserts 2 stall cycles when move instructions that satisfy all of the following
characteristics are executed:
The inserted stall cycles effectively make these instructions 3-cycle instructions. The stalls are inserted so
that the register is updated by the addressing mode after being used as the source register in the move
instruction. Example 10-7 shows three instructions that fall into this category.
This type of dependency occurs whenever an address pointer register is used as the source in a store
instruction, while, within the same instruction, the same pointer is being updated (modified) by an
addressing mode. There is no dependency if the register is used as a destination in the move instruction.
Example 10-8 on page 10-31 shows this case and other instances where there is no dependency.
10-30
Pipeline
Stage
OP2
EX2
AG
EX
P1
P2
ID
IF
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The instruction is a move from a register to data memory.
The source of the move is an AGU register (R0–R5, N, or SP).
The AGU register that is used for the effective address is the same AGU register that is used as the
source of the move instruction.
The addressing mode is one of the three post-update addressing modes:
— Post-increment
— Post-decrement
— Post-update by offset register
n1
Instructions with Inherent Stalls
MOVE.W
MOVE.W
MOVE.W
1
n2
n1
2
Example 10-7. MOVE Instructions That Introduce Stalls
n3
n2
n1
3
R1,X:(R1)+
N,X:(N)-
R5,X:(R5)+N
Table 10-7. AGU Pipeline With No Dependencies
movu
n4
n3
n2
4
DSP56800E Core Reference Manual
movu
mov
n5
n4
n3
5
movu
mov
mov
n6
n5
n4
6
; R1 stored with R1 post-update
; N stored with N post-update
; R5 stored with R5 post-update
Instruction Cycle
movu
mov
mov
add
n7
n6
n5
7
mov
mov
mov
add
n7
n6
—
8
•
mov
mov
add
tfra
n7
—
9
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mov
mov
add
tfra
10
—
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Freescale Semiconductor
mov
mov
tfra
11
—
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mov
tfra
—
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mov
—
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—
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