dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 585

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

ORC
Operation:
#xxxx + X:<ea> → X:<ea>(no parallel move)
#xxxx + D → D(no parallel move)
where + denotes the logical inclusive OR operator
Implementation Note:
Description: Perform a logical OR operation on a 16-bit immediate data value with the destination operand (D), and
Example:
Explanation of Example:
Condition Codes Affected:
Note:
Instruction Fields:
Freescale Semiconductor
This instruction is implemented by the assembler as an alias to the BFSET instruction, with the 16-bit
immediate value used as the bit mask. This instruction will dis-assemble as a BFSET instruction.
store the results back into the destination. C is also modified as described in “Condition Codes Affect-
ed.” This instruction performs a read-modify-write operation on the destination and requires two des-
tination accesses.
ORC
Prior to execution, the 16-bit X memory location X:$7C30 contains the value $00AA. Execution of the
instruction performs a logical OR of $00AA and the mask (immediate value $5555) and stores the re-
sult in X:$7C3A. The C bit is not set because all mask bits are not set.
For destination operand SR:
For other destination operands:
L
C
If all bits in the mask are cleared, the instruction executes two NOPs and sets the C bit.
Refer to the section on the BFSET instruction for legal operand and timing information.
Before Execution
X:$7C30
LF
15
— Set if data limiting occurred during 36-bit source move
— Set if all bits specified by the mask are set
SR
P4
14
For this destination only, the C bit is not updated as is done for all other destination operands
All SR bits except bits 14–10 are updated with values from the bitfield unit.
Bits 14–10 of the mask operand must be cleared.
Cleared if at least 1 bit specified by the mask is not set
#$5555,X:$7C30
13
P3
Logical Inclusive OR Immediate
P2
12
00AA
0300
MR
P1
11
P0
10
Instruction Set Details
I1
9
Assembler Syntax:
ORC
ORC
I0
8
; OR with immediate data
SZ
7
6
L
5
E
After Execution
X:$7C30
#iiii,X:<ea>
#iiii,D
U
4
CCR
SR
N
3
2
Z
55FF
0300
V
(no parallel move)
(no parallel move)
1
C
0
ORC
A-241