dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 289

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Pipeline During Interrupt Processing
When an interrupt request is asserted, the interrupt controller takes 2 cycles to arbitrate between interrupts
and to send an interrupt request to the core. During this time, the pipeline continues to function normally.
When the core recognizes an interrupt request, as in cycle #5 in Figure 10-2 on page 10-8, the transition to
the exception processing state begins. Any instructions in the pipeline that have not yet been decoded are
replaced with NOPs, and the JSR instruction is fetched from the interrupt vector table.
Upon entering the interrupt service routine after executing the JSR instruction, the core returns to the
normal processing state, and the CCPL has been updated to reflect the new priority level.
When the interrupt handler completes (by executing the RTI instruction), control returns to the interrupted
program. The return address, which is saved on the stack by the JSR, points to instruction n2, since the PC
was frozen as soon as the interrupt was recognized. The PC was not updated to point past n2, even though
instructions n2–n4 had already begun to be fetched.
10.3.2
The RTID Instruction
In the example interrupt processing pipeline that is presented in Figure 10-2 on page 10-8, most of the time
that is needed to execute the (admittedly short) interrupt routine is taken up by the JSR and RTI
instructions. Because the RTI instruction manipulates the software stack and causes execution flow to
change, it takes several cycles to execute. To help reduce the overhead that is required in processing an
interrupt, an alternative to the RTI instruction is provided: the delayed return from interrupt (RTID).
The RTID instruction performs the same function as RTI, but it reduces overhead by executing the
instructions in the 3 subsequent program words before returning control to the interrupt program. These
instruction words, or “delay slots,” must always be filled. If it is not possible to fill all of the delay slots
with useful instructions, then NOP instructions must be placed in the unfilled slots. See Section 4.3,
“Delayed Flow Control Instructions,” on page 4-12 for more information on the RTID instruction.
The interrupt processing pipeline when RTID is used is given in Figure 10-3 on page 10-10. Note the
difference between Figure 10-3 and Figure 10-2 on page 10-8 from cycle #13 onward: the di0–di2
instructions are executed before control returns to instruction n2.
Freescale Semiconductor
Instruction Pipeline
10-9