dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 15

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

List of Figures
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 1-5
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 3-11
Figure 3-12
Figure 3-13
Figure 3-14
Figure 3-15
Figure 3-16
Figure 3-17
Figure 3-18
Figure 3-19
Figure 3-20
Figure 3-21
Figure 3-22
Figure 3-23
Figure 3-24
Freescale Semiconductor
DSP56800E Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Example of Chip Based on DSP56800E Core . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Analog Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Mapping DSC Algorithms into Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
DSP56800E Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
DSP56800E Dual Harvard Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . 2-4
DSP56800E Chip Architecture with External Bus . . . . . . . . . . . . . . . . . . . . . . . 2-5
DSP56800E Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Example of Chip Based on DSP56800E Core . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
DSP56800E Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Single Parallel Move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Dual Parallel Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Data Alignment in Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Supported Data Types in Data Registers (X0, Y1, Y0) . . . . . . . . . . . . . . . . . . 3-14
Data Alignment in 24-bit AGU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Data Alignment in 16-Bit AGU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Structure of Byte and Word Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Accessing a Word with a Word Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Correct Storage of 32-Bit Value in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Accessing a Long Word Using an Address Register . . . . . . . . . . . . . . . . . . . . 3-20
Accessing a Long Word Using the SP Register . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Accessing a Byte with a Word Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Accessing a Byte with a Byte Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Address Register Indirect: No Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Address Register Indirect: Post-Increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
Address Register Indirect: Post-Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
Address Register Indirect: Post-Update by Offset N . . . . . . . . . . . . . . . . . . . . 3-32
Address Register Indirect: Indexed by Offset N. . . . . . . . . . . . . . . . . . . . . . . . 3-33
Address Register Indirect: Indexed by 3-Bit Displacement . . . . . . . . . . . . . . . 3-34
Address Register Indirect: Indexed by 6-Bit Displacement . . . . . . . . . . . . . . . 3-35
Address Register Indirect: Indexed by 16-Bit Displacement . . . . . . . . . . . . . . 3-36
Address Register Indirect: Indexed by 24-Bit Displacement . . . . . . . . . . . . . . 3-37
Immediate Addressing: 5-Bit Immediate Data to Accumulator . . . . . . . . . . . . 3-38
List of Figures
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