dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 271

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Two types of interrupt processing routines are supported: normal and fast. Normal interrupt processing is
supported for all types of interrupts, but it involves a certain amount of overhead. Fast interrupt processing
requires substantially less overhead, but it is only available for level 2 interrupts. The type of interrupt
processing that will be performed is determined by the opcode that is located in the vector for a given
interrupt and by the priority level of the interrupt source. If the instruction is a JSR, normal interrupt
processing occurs. If it is any other instruction and level 2, fast interrupt processing is used. The case
where the first instruction is not a JSR and the priority level is 0, 1, or 3 is not permitted.
9.3.2.1
Under most circumstances, normal interrupt processing is used to handle an interrupt or exception. When
an interrupt occurs, the following occurs:
The interrupt routine that is located at the target address of the JSR is then executed. Be careful in the
interrupt handler routine to save any registers that will be used; otherwise, the operation of the interrupted
program may be affected. The status register, however, is automatically saved when an interrupt occurs, so
it does not need to be saved by the handler.
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1. The currently executing instruction is allowed to complete, and all subsequent instructions
2. The program counter is frozen.
3. The CCPL is raised to be one higher than the level of the current interrupt.
4. The program controller fetches the JSR instruction that is located at the vector for this
5. The JSR instruction is executed, saving the original program counter and status register on
are flushed from the pipeline.
interrupt, and then it unfreezes the PC.
the software stack.
Normal Interrupt Processing
Vector #23
Vector #22
.
.
.
Figure 9-1. Interrupt Vector Table
Processing States
Handler Address
Interrupt Vector
Handler Address
Table
JSR
JSR
.
.
.
.
.
.
JSRs to Normal Interrupt
Handler Routines
Exception Processing State
9-5