dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 294

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dsp56800e

Manufacturer Part Number
dsp56800e
Description
16-bit Digital Signal Controller Core
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Instruction Pipeline
10.3.6
Interrupting a Fast Interrupt Service Routine
Fast interrupt service routines can be interrupted by a level 3 interrupt. However, the first few instructions
in a fast interrupt service routine cannot be interrupted, even if a level 3 interrupt is received. Figure 10-6
on page 10-15 shows the fast interrupt pipeline and the point at which interrupts are re-enabled and
subsequent interrupts can be arbitrated. Even if a level 3 interrupt is received prior to this point in the
pipeline, it is not sampled by the interrupt arbiter until instruction cycle #13 (as shown in the figure), so at
least 7 clock cycles in the fast interrupt routine are executed without being interrupted. Note that the
instructions in the FRTID’s 2 delay slots cannot be interrupted.
10-14
DSP56800E Core Reference Manual
Freescale Semiconductor

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