dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 112

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Instruction Set Introduction
Table 4-42 on page 4-49 shows all the registers and addressing modes that are allowed in a dual read
instruction, one of the DSP56800E’s parallel move instructions. Based on the entries in the summary tables
for the MOVE, MACR, and ADD instructions, as well as the information contained in Table 4-42, we see
that the instructions in Example 4-4 are allowed.
The instruction summary tables can also be used to determine if a particular instruction is not allowed.
Consider the instruction in Example 4-5.
Using the information in Table 4-31 on page 4-30 and Table 4-42 on page 4-49, we know that this
instruction is invalid for the following reasons:
4.4.2
There are many different register fields that are used within the instruction summary tables. The following
tables outline the notation that is used to specify legal registers.
Table 4-15 shows the register sets that are available for the most important move instructions. Whenever
the supported set of registers varies due to whether the set is the source or destination of an operation, the
difference is noted. Register fields that are used in conjunction with AGU move instructions are listed in
Table 4-16 on page 4-17.
In some cases, the notation that is used for specifying an accumulator determines whether or not saturation
is enabled when the accumulator is being used as a source in a move or parallel move instruction. Refer to
Section 5.8.1, “Data Limiter,” on page 5-39 and Section 5.2, “Accessing the Accumulator Registers,” on
page 5-6 for more information.
4-16
Register Field
•
•
•
•
•
•
(source)
HHH
The ADD instruction only takes two operands, not three.
The pointer R2 is not allowed for the first memory read.
The post-decrement addressing mode is not available for the first memory read.
The X0 register cannot be a destination for the first memory read.
The post-update–by–N addressing mode is not allowed for the second memory read; only the
post-increment, post-decrement, and post-update–with–N3 addressing modes are allowed.
The Y0 register cannot be a destination for the second memory read.
Register Field Notation
MOVE.W
MACR
ADD
ADD
Table 4-15. Register Fields for General-Purpose Writes and Reads
Registers in This
A1, B1, C1, D1
X0, Y0, Y1
X0,Y1,A
Y0,B
X0,Y1,A
Field
DSP56800E Core Reference Manual
Example 4-5. Invalid Instruction
Example 4-4. Valid Instructions
X:(R0)+,Y0
X:(R1)+N,Y1
X:(R1)+N,Y0
X:(R2)-,X0
Seven data ALU registers—four 16-bit MSP portions of the accumula-
tors and three 16-bit data registers used as source registers. Note the
usage of A1, B1, C1, and D1.
This field is identical to the FFF1 field.
X:(R3)+,X0
X:(R3)-,X0
X:(R3)+,X0
X:(R3)+N,Y0
Comments
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